[00:00:03] Speaker 01:
The first case for argument this morning is 182123, Netlist versus SK Hynex.

[00:00:10] Speaker 01:
Ready whenever you are, sir.

[00:00:17] Speaker 00:
Good morning, Your Honor.

[00:00:18] Speaker 00:
May it please the Court?

[00:00:20] Speaker 00:
Tom Wimbiscus on behalf of Netlist.

[00:00:22] Speaker 00:
The board's decisions are problematic with error for three primary reasons.

[00:00:26] Speaker 00:
I'll touch on those, and then I'll go into those in detail.

[00:00:29] Speaker 00:
First, the board denied Netlist its procedural rights, because Hynix failed to disclose the basis for any alleged and inherent theory in its petition, and later expanded upon that theory on reply by presenting new attorney argument without expert support and raising new factual issues.

[00:00:48] Speaker 00:
Second, the board erred in its inherency analysis

[00:00:52] Speaker 01:
With respect to- Well, before, can I just distract you a minute?

[00:00:54] Speaker 01:
Honestly, I'm only speaking for myself.

[00:00:56] Speaker 01:
But I'd like you to focus, if you could, at least initially on this test mode theory piece of it.

[00:01:01] Speaker 00:
Yes, Your Honor.

[00:01:02] Speaker 00:
Okay.

[00:01:02] Speaker 00:
That would be helpful to me.

[00:01:04] Speaker 00:
Sure.

[00:01:04] Speaker 01:
And that's... And that involves the BIST controller.

[00:01:06] Speaker 01:
Is it simply the question of whether the BIST controller satisfies the system memory controller cited in the claims?

[00:01:14] Speaker 00:
It's, in our view, more complicated than that, Your Honor.

[00:01:18] Speaker 00:
First, there is an aspect of it as to whether the BIST controller does satisfy the system memory controller.

[00:01:24] Speaker 00:
And with respect to that, a few points.

[00:01:26] Speaker 00:
Your Honor, first of all,

[00:01:29] Speaker 00:
final written decision site in a one sentence statement said that the Avrabuj discloses that the BIS controller produces or generates control signals for the memory modules and then labeled that essentially as the system memory controller.

[00:01:44] Speaker 00:
But Avrabuj, I'm sorry, but the one site that the final written decision made was to the institution decision which recognized that it's the sequencer that produces

[00:01:59] Speaker 00:
the control signals that are used to manage the flow of data to and from the memory devices.

[00:02:05] Speaker 00:
The BIS controller doesn't operate alone to accomplish that effect.

[00:02:10] Speaker 00:
It must work with the sequencer.

[00:02:12] Speaker 00:
The sequencer does the processing of these high-level commands, and from those, it processes the commands, does parsing, and then attributes the timing.

[00:02:22] Speaker 04:
I have a very... I have laryngitis, so you're going to have to listen, and if you can, I'll try to repeat it.

[00:02:28] Speaker 00:
Sure.

[00:02:29] Speaker 04:
My problem with that argument is the BIST controller actually controls the sequencer itself as well.

[00:02:35] Speaker 04:
So why isn't the BIST controller therefore controlling all of it?

[00:02:39] Speaker 00:
Because the BIST controller is the alleged system memory controller and it operates with the... With.

[00:02:47] Speaker 04:
It controls the sequencer as the upper bush reference.

[00:02:50] Speaker 00:
It controls in the sense that it issues high-level commands, but those high-level commands don't in and of themselves manage the flow of data to and from the memory.

[00:02:59] Speaker 01:
The sequencers control the flow of data, but that's simply based on signals that are received from the BIS controller, right?

[00:03:06] Speaker 00:
That are processed, parsed, and then the sequencer alone

[00:03:11] Speaker 00:
imparts the timing such that those signals can be used once parsed to manage the flow of data to and from memory.

[00:03:17] Speaker 00:
The high level commands from the disk controller are not capable of doing that.

[00:03:21] Speaker 00:
Of doing what, precisely?

[00:03:23] Speaker 01:
Of managing the timing?

[00:03:24] Speaker 00:
Managing the flow of data to and from memory.

[00:03:27] Speaker 00:
And if you turn to the analysis with respect to that, petitioner's expert, Dr. Mazunder, doesn't add his paragraph 70 at Appendix 662,

[00:03:40] Speaker 00:
He has one paragraph directed to this issue, and he never once uses the construction manages the flow of data to and from the memory devices.

[00:03:50] Speaker 00:
He just puts the label on it and says these high-level commands are a system memory controller.

[00:03:55] Speaker 00:
But he clarifies also then in paragraph.

[00:03:57] Speaker 00:
So he doesn't apply the claim construction.

[00:04:00] Speaker 00:
And neither did the board in that respect.

[00:04:03] Speaker 00:
They just relied on Dr. Masunder's analysis, which is a high-level command that has to be processed

[00:04:10] Speaker 00:
And you have to have timing associated with that.

[00:04:13] Speaker 00:
And that's all done in a sequencer.

[00:04:15] Speaker 01:
But as you refer to it, there was an agreed upon claim construction.

[00:04:18] Speaker 01:
It was agreed upon.

[00:04:19] Speaker 01:
Let me finish my question.

[00:04:21] Speaker 01:
I'm sorry.

[00:04:21] Speaker 01:
And that construction was a device that manages the flow of data to and from the memory of a system, right?

[00:04:29] Speaker 00:
Yes.

[00:04:30] Speaker 01:
That's kind of broad.

[00:04:31] Speaker 01:
There's no reference to particular activity with respect to timing and so forth.

[00:04:36] Speaker 00:
The parties, but not their experts,

[00:04:38] Speaker 00:
I'd submit disputed whether or not that implicitly requires accounting for timing characteristics.

[00:04:44] Speaker 00:
And the testimony from both parties and the extrinsic evidence relied upon by petitioner's expert was textbook evidence that said that managing the flow of data requires accounting for timing characteristics and that a system memory controller operates and does that by providing address control and data signals.

[00:05:05] Speaker 00:
And it's petitioner's expert who quoted

[00:05:07] Speaker 00:
The excerpt from the Baker textbook, exhibit 1008, and he quoted it and then he highlighted select portions of that and included in that highlight is the notion that a system memory controller, I'm sorry, the memory controllers manage the movement of data into and out of DRAM devices and it goes on to say, while accounting for timing characteristics.

[00:05:30] Speaker 00:
Netlist expert agreed with that so there's a dispute about the complete meaning of Manage the flow of data to and from memory devices whether that requires the accounting and it's and We submit that there should have been a further claim construction analysis to look at all of this in strength and in extrinsic So did you go to the board and said your complaint construction is inadequate and we need another we pointed we point out in our patent owner response that

[00:05:57] Speaker 00:
Both parties came in with the proposed claim construction, but during the proceeding it became clear that there's a dispute about the meaning of that proposed construction and in our view that's under Teva The board should engage in further subsidiary fact findings a view of all this extrinsic evidence which both parties pointed to which says as I just read

[00:06:20] Speaker 00:
Managing the flow of data which comes requires accounting for timing characteristics now.

[00:06:25] Speaker 00:
We're dealing with a term of art here Acknowledged by both parties both parties agree That this construction comes out of these extrinsic evidence textbooks that manage the flow of data didn't come out of the spec it came out of the extrinsic evidence and we submit that the board should have considered all the extrinsic evidence and

[00:06:45] Speaker 00:
and not just portions of it, it should have engaged in more thorough.

[00:06:48] Speaker 01:
So what is the timing?

[00:06:50] Speaker 01:
And you say what their expert said was inadequate?

[00:06:53] Speaker 01:
Pardon me, ma'am?

[00:06:54] Speaker 01:
You said what their expert said was inadequate with respect to timing?

[00:06:59] Speaker 00:
Their expert acknowledged that timing is required to account for managing the flow.

[00:07:05] Speaker 00:
And that's what the expert pulled and highlighted from the Jacobs textbook, exhibit 1008,

[00:07:11] Speaker 00:
And then he also backstopped that with Exhibit 1009, another textbook where he exemplified managing the flow of data from a system memory controller requires address control and data signals.

[00:07:24] Speaker 00:
None of those are coming out of the BIST.

[00:07:27] Speaker 00:
And none of the timing is from the BIST.

[00:07:30] Speaker 00:
Now, I think it was a last effort by

[00:07:35] Speaker 00:
Heineck's in their last brief tried to imply that the This controller manages the timing because it directs the sequencer, but that's just flatly inconsistent with the the reference Avrabujed paragraph appendix pair appendix page 744 paragraph 30 or rejected your construction that timing was part of the requirement in the patent owner response and

[00:08:02] Speaker 04:
board rejected your construction about timing.

[00:08:07] Speaker 04:
So you only get to Averbouge doesn't disclose the bis controller modulating timing if we accept the premise that the board's claim construction itself is wrong.

[00:08:17] Speaker 00:
Yes, and our position is that the board should have engaged in further subsidiary fact finding on this dispute over the meaning of manage the flow of data.

[00:08:27] Speaker 00:
Does that require into and out of memory devices?

[00:08:30] Speaker 00:
Does that require timing?

[00:08:32] Speaker 00:
Accounting for time and we submit that all the evidence from from the extrinsic evidence that was submitted Yes, I'm just trying to understand is your entire argument with regard to best hinge on us having to accept your claim construction No, no part of it does I think there's two points on the test mode the first is that the the best is at best one link in a chain

[00:08:54] Speaker 00:
And akin to a wire emitting a signal, a wire emitting a signal doesn't itself manage the flow of data.

[00:09:01] Speaker 00:
The BIST only operates by emitting high-level commands.

[00:09:05] Speaker 00:
It's the sequencer.

[00:09:06] Speaker 03:
Just to be curious, you think wires emit signals?

[00:09:09] Speaker 00:
Pardon me?

[00:09:09] Speaker 03:
Just curious, you think wires emit signals?

[00:09:11] Speaker 00:
Well, in the context of the board's initial clamp construction as a device that emits a signal, an amplifier wire.

[00:09:18] Speaker 04:
And you think the BIST is just a wire?

[00:09:20] Speaker 00:
No, I'm saying if you take that analogy

[00:09:24] Speaker 00:
The extreme, just a device that admits a wire or other device that admits a signal doesn't achieve management of the flow.

[00:09:33] Speaker 04:
But you think a wire admits a signal.

[00:09:35] Speaker 04:
I'm just completely baffled.

[00:09:37] Speaker 00:
No, I'm referring to the board's initial claims.

[00:09:41] Speaker 04:
The board didn't say a wire.

[00:09:42] Speaker 00:
No, the board didn't say a wire.

[00:09:43] Speaker 00:
It said a device that admits a signal, I believe.

[00:09:46] Speaker 04:
Yes, correct, because a wire can't admit a signal.

[00:09:49] Speaker 04:
That's technical nonsense.

[00:09:50] Speaker 00:
Well, I think in the context of how I was viewing this, Your Honor, that it takes more than an admission of a signal to manage the flow of data to and from memory.

[00:10:00] Speaker 00:
You have to account for timing.

[00:10:01] Speaker 00:
And that the BIST is but a link in the chain.

[00:10:06] Speaker 00:
And the sequencer is part of that process.

[00:10:10] Speaker 00:
But the sequencer is separately claimed in here in the read to be the module controller, not the system memory controller.

[00:10:17] Speaker 00:
So it's part of the read.

[00:10:19] Speaker 00:
Two points with respect to that argument on test mode.

[00:10:22] Speaker 00:
One is, on the read, there's a dispute because the system memory controller, the BIS, would require the sequencer to unpack process and account for timing.

[00:10:33] Speaker 00:
And that's consistent with the submission on the record of what it means to manage the flow of data to and from memory.

[00:10:40] Speaker 00:
But secondly, we submit that the board

[00:10:42] Speaker 00:
should have engaged in subsidiary fact-finding because there is a dispute over the complete meaning of manage the flow of data to and from the memory devices.

[00:10:52] Speaker 01:
So you've said repeatedly the board should have engaged in subsidiary fact-funding.

[00:10:56] Speaker 01:
Are you saying this is a question part of a substantial evidence review, or are you saying this is an error in claim construction?

[00:11:02] Speaker 00:
I'm saying it's an error of claim construction.

[00:11:04] Speaker 00:
Under TEVA, where the parties cannot agree on their complete meaning of the term, that's an issue of law for the court.

[00:11:13] Speaker 00:
And what is the meaning of that?

[00:11:14] Speaker 00:
And in this case, it's clear that this is a term.

[00:11:16] Speaker 01:
So the board was compelled, required in your view, to reconstitute the term that was.

[00:11:21] Speaker 00:
That the parties to the construction on this on that particular issue yes on test mode There was no construction wrestling with the details of whether or not manage the flow of data Requires accounting for timing characteristics, and it's in the extrinsic evidence whether there's testimony from both parties experts to that effect And that was implicit in that the construction proposed construction

[00:11:46] Speaker 01:
We're into your rebuttal, so why don't we reserve it on the other side.

[00:11:51] Speaker 01:
I'm sorry?

[00:11:51] Speaker 01:
We're into your rebuttal time.

[00:11:53] Speaker 01:
Thank you.

[00:11:53] Speaker 01:
So we'll reserve it on the other side.

[00:11:56] Speaker 01:
Thank you.

[00:12:04] Speaker 02:
Good morning, Your Honors.

[00:12:05] Speaker 02:
May it please the court, Joe McAuliffe for SK Hynex.

[00:12:08] Speaker 02:
The board properly found that Avrabouj anticipates... Can I just... I'm sorry.

[00:12:12] Speaker 01:
Can we just follow up on what we were discussing with your friend?

[00:12:15] Speaker 01:
And that is, is it your position that the BISC controller does not have to do anything with timing, or that it in fact does?

[00:12:22] Speaker 02:
It does not.

[00:12:24] Speaker 02:
To be a system memory controller, it has to be a device that manages flow of data to and from the memory.

[00:12:29] Speaker 02:
That was the agreed interpretation.

[00:12:32] Speaker 02:
Managing timing could be an example of that management, but other things could be management as well.

[00:12:37] Speaker 02:
And here it's undivided really that the bis controller does perform a management function, in fact a very high level management function, by determining which algorithms and commands to send to the rest of the system like the sequencer.

[00:12:50] Speaker 02:
And thereby control the testing of the memory chips themselves by determining when and what patterns of data are written into the memory and read out

[00:13:02] Speaker 02:
So as to perform the self-test so that was a finding of fact.

[00:13:06] Speaker 02:
I think by the board that the bis controller Satisfied that agreed claim construction certainly substantial evidence in the record of that we cited several Paragraphs from the average reference we have our experts testimony.

[00:13:24] Speaker 02:
It's a finding of fact

[00:13:25] Speaker 02:
supported by substantial evidence.

[00:13:28] Speaker 02:
Now, they have asked in this court and below for a more limited interpretation, but it's odd because in their preliminary response, they agreed.

[00:13:38] Speaker 02:
In fact, the only thing they said about the interpretation of system memory controller in their preliminary response, which is at the appendix page 121, is, quote, patent owner agrees that a system memory controller is a device that manages the flow of data to and from the memory.

[00:13:54] Speaker 02:
Interestingly, even more, in the patent owner response, they actually asserted that that interpretation of system memory controller is what a person of ordinary skill in the art would understand the phrase to mean.

[00:14:07] Speaker 02:
So they admitted that the ordinary meaning of that term is our interpretation.

[00:14:15] Speaker 02:
So that, I think, unless they can do it.

[00:14:17] Speaker 04:
But he says implicit and managing the flow of data is timing.

[00:14:23] Speaker 04:
and that both experts agreed on that.

[00:14:25] Speaker 04:
So he says when we agreed to that construction, given that both experts incorporated timing as a condition, we understood that to be part of what we're agreeing to.

[00:14:36] Speaker 04:
At least that's what I understand his argument to be.

[00:14:38] Speaker 02:
That may be his argument.

[00:14:39] Speaker 02:
Our expert never agreed that that was a condition of management.

[00:14:43] Speaker 02:
It might be an example of management dealing with timing.

[00:14:46] Speaker 02:
But we very clearly did not put timing in our proposed construction, and they very clearly agreed

[00:14:52] Speaker 02:
to our proposed construction that didn't say anything about timing.

[00:14:55] Speaker 02:
So I don't understand how you can say now.

[00:14:58] Speaker 02:
Well, no, we always expected these words to mean timing, even though they didn't say anything about timing.

[00:15:05] Speaker 04:
So I think the interpretation, and as far as the subsidiary fact-finding them, I thought- Well, would managing flow require, if not timing precisely, at least ordering?

[00:15:17] Speaker 02:
Well- Ordering.

[00:15:19] Speaker 04:
Ordering.

[00:15:20] Speaker 04:
If I manage the flow to the bathroom,

[00:15:22] Speaker 04:
I'm not sending everybody in at once.

[00:15:25] Speaker 04:
You're ordering how they access the data.

[00:15:27] Speaker 02:
I don't know if I can agree it would require it.

[00:15:28] Speaker 02:
I would certainly agree that could be an example of it.

[00:15:30] Speaker 02:
But I would also point out that the BIS controller does that, Your Honor.

[00:15:34] Speaker 02:
It's the one that determines what commands and when.

[00:15:37] Speaker 04:
What do you think managing the flow of data means?

[00:15:41] Speaker 04:
How do you achieve management of the flow of data?

[00:15:45] Speaker 04:
Not just managing data, but the flow of data.

[00:15:48] Speaker 04:
I mean, that flow word sort of makes me think of a river.

[00:15:51] Speaker 02:
Yeah, sure.

[00:15:52] Speaker 02:
Well, the best controller manages, first of all, when that's going to happen for self-test purposes.

[00:15:57] Speaker 02:
And it's also going to

[00:15:59] Speaker 02:
to manage the algorithms that are used, including the bits.

[00:16:03] Speaker 02:
So my understanding of this technology, and I think there's a little in the record on this, that different patterns of bits can be used to test these.

[00:16:10] Speaker 01:
So at some high level, it does control timing to a certain extent, just as the way it operates.

[00:16:17] Speaker 01:
It's high level control on testing and communicating the algorithms.

[00:16:21] Speaker 01:
So that's why I started off by asking you what your position was that, no, it doesn't do timing, but we don't need timing, or kind of depends on how high level you're viewing the limitation of timing.

[00:16:37] Speaker 02:
It would be the latter.

[00:16:38] Speaker 02:
I mean, I don't think controlling timing is required by the agreed upon construction.

[00:16:43] Speaker 02:
But I do, as I said before, I think it's an example of managing the flow of data.

[00:16:48] Speaker 02:
And yes, you could conclude on this record here that the BIST controller does exactly that, because it does determine the algorithms used and when to use them.

[00:16:58] Speaker 02:
And so it manages the flow of data in that sense.

[00:17:04] Speaker 02:
These issues, whether

[00:17:06] Speaker 02:
The finding that the BIST controller is a system memory controller is supported by substantial evidence.

[00:17:13] Speaker 02:
And whether the claim interpretation is correct, and I think it's undisputably correct here.

[00:17:18] Speaker 04:
If we agree with you that the BIST controller... Forget it, you're not technically the guy arguing that.

[00:17:25] Speaker 04:
Go ahead, keep going.

[00:17:26] Speaker 02:
I was just going to say, this is all you have to decide for this case, right?

[00:17:28] Speaker 02:
Because the board found anticipation on two alternative bases, test mode and normal mode.

[00:17:33] Speaker 02:
Unless you have more questions on test mode, I'm happy to move to normal mode.

[00:17:41] Speaker 02:
He did not, so I'm happy to, if you're not interested.

[00:17:44] Speaker 04:
I mean, if you want to open the door to him addressing something on rebuttal that he otherwise can't address, that's your problem.

[00:17:49] Speaker 02:
I will see the rest of my time unless there are more questions.

[00:17:52] Speaker 02:
Thank you.

[00:17:58] Speaker 00:
Your Honor, I'd like to revisit

[00:18:00] Speaker 00:
specifically what the evidence was on what it means to manage the flow of data.

[00:18:04] Speaker 00:
And take you to appendix pages 662 through 665, that's Dr. Mazander, INIX's expert, and on paragraph 70, he doesn't at all use or apply the claim construction to manage the flow of data to and from memory devices.

[00:18:21] Speaker 00:
You won't find it there.

[00:18:23] Speaker 00:
And where you will find it is in the analysis with respect to normal mode signals, which he says involve a use of address control and data signals.

[00:18:36] Speaker 04:
I guess I'm confused.

[00:18:38] Speaker 04:
He is describing, as an expert should, how he understands the BIST controller to operate in the context of the prior art.

[00:18:46] Speaker 04:
Are you saying the board can't read

[00:18:49] Speaker 00:
analysis and from that conclude that the best controller therefore Processes and what I'm saying is that we're saying he has to have the magic claim words or his testimony I'm saying he made an argument pertaining to high-level command signals where he didn't apply report to apply the the

[00:19:13] Speaker 00:
agreed claim construction of managing the flow of data to and from memory devices.

[00:19:17] Speaker 04:
Yes, but he describes what the BIST controller does, which sounds like managing data to me the way he describes it in BearCraft 7.

[00:19:24] Speaker 04:
So are you saying the board can't rely on his articulation and conclude

[00:19:29] Speaker 04:
that meets the managing data requirement?

[00:19:31] Speaker 00:
It can if in fact it does meet the definition of manage the flow and flow requires interacting with the memory devices and where the expert gets into the meat about what it means to manage the flow is paragraph 71 and 72 and 73 and on paragraph 72 he says that manages the flow of data to and from the system

[00:19:54] Speaker 00:
is shown here, and he takes a quote, and he quotes the Jacobs textbook, exhibit 1008 of page 97, 497, where he references and highlights the text he selected.

[00:20:06] Speaker 00:
Memory controllers manage the movement of data into and out of DRAM devices while ensuring for, among other things, timing characteristics.

[00:20:14] Speaker 00:
That's what it means to manage the flow of data, not just a cause and effect in a circuit,

[00:20:20] Speaker 00:
where an upstream circuitry has an impact downstream.

[00:20:25] Speaker 00:
This is managing the flow of data to and from the memory devices.

[00:20:29] Speaker 00:
And that requires accounting for time.

[00:20:31] Speaker 00:
And you'll find it right here in his textbook.

[00:20:35] Speaker 00:
And he goes on to further delineate that in paragraph 73, where he cites another extrinsic evidence piece, exhibit 1009, where he shows address, data, and control signals are used to achieve that.

[00:20:49] Speaker 00:
You won't find address control and data signals.

[00:20:51] Speaker 00:
and from the BIST controller, those are just high-level commands.

[00:20:54] Speaker 00:
So I'll grant you there is a cause and effect, if you will, but the effect, the implementation of the flow requires not just the BIST, but also the sequencer.

[00:21:03] Speaker 00:
It's those two together that are needed to manage the flow of data to and from the memory devices.

[00:21:10] Speaker 00:
Otherwise, you just have a cause and effect situation where one upstream component has an effect of something downstream in an electrical circuit, and that's not

[00:21:21] Speaker 00:
That's too broad.

[00:21:22] Speaker 00:
It doesn't reflect managing the flow of data any more than perhaps powering up the circuit.

[00:21:29] Speaker 00:
What the expert made clear here is that managing the flow as interpreted by a person's skill in the art, which is why he said he submitted this and quoted this particular text, requires accounting for timing characteristics.

[00:21:44] Speaker 00:
And Netlist expert agreed.

[00:21:46] Speaker 00:
The bottom line is the court didn't wrestle with that.

[00:21:50] Speaker 00:
gave it short shrift, I'm sorry, the board, and reasoned that it's not part of the claim construction.

[00:21:55] Speaker 00:
But in our view, it is a part of, it's implicit in the claim construction.

[00:21:59] Speaker 00:
And the board should at least engage in some consideration and fact finding to see if this agreed upon term of art should be viewed as implicating timing characteristics.

[00:22:13] Speaker 00:
You're beyond your time.

[00:22:14] Speaker 00:
Thank you, Your Honor.

[00:22:15] Speaker 00:
We thank both sides.

[00:22:19] Speaker 01:
The next case for argument this morning is 18-2357.

[00:22:24] Speaker 01:
Again, Netlist versus S.K.

[00:22:26] Speaker 01:
Hyman.