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The United States Court of Appeals for the Federal Circuit is now open and in session.

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God save the United States and this honorable court.

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Good morning.

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The first case for argument this morning is 20-1925 FGSRC versus Microsoft Corporation.

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Mr. Key, whenever you're ready.

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Thank you, Your Honor, and may it please the court.

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My name is Cecil Key on behalf of the patent owner and appellant FGSRC.

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I'll be focusing my argument today on the three erroneous claim constructions adopted by the board that patent owner believes must be reversed because they are contrary to the intrinsic evidence and because rather than clarifying, they actually introduce unneeded ambiguity.

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And we'll reserve, subject to any questions, excuse me, we'll defer to the brief, subject to any questions on the other issues raised.

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As a brief bit of background, the two patents that issue here, the 324 and 800, are directed to inventions in the field of high-performance computing.

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And that is a field in which the patent owner's predecessor and founder, Seymour Cray, was a renowned expert.

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In fact, the SRC and the patent owner's name is a result of Mr. Cray.

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And FCSRC's technology is implemented in drone surveillance and targeting used by the US military to protect our men and women serving throughout the world.

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Mr. Key, could I just interrupt you there because time is short.

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Let me just ask you, the first claim construction issue involves computational loop.

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Can you just articulate to us briefly what the difference is between your construction and the one that your friends on the other side in the board adopted?

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What's the difference?

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Yes, Your Honor.

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The difference is that our position is that the construction should include the qualifier over a dimension of data so that the full construction will read a set of computations that is executed repeatedly over a dimension of data either a fixed number of times or until some condition is true or false.

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And the basis for that comes from both the claims and the specification, Your Honor.

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it is clear that the computational loops are computations that are to be performed over a dimension of data.

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It's shown in figure 4B of the 324 patent, for example, and then in the specification that states that there are two loops operating a number of times on each dimension of data.

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Let me ask you about the specification.

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Am I correct that under the board's BRI construction,

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the examples in the specification that are per datum are not excluded, right?

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That is correct, Your Honor.

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That is correct.

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They are not excluded.

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The issue that we raise is simply that we believe that given the board's analysis and application, that adding the over dimension of data further clarifies precisely what the computational loop, the structure and performance is

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for these patents.

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I think, unfortunately, without that further clarification, it appears that the board seemed to consider that just sort of any loops might be considered computational loops.

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And we think that this is simply a matter of adding further clarification.

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Council, this is Judge O'Malley.

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Part of my problem is that you kept changing, in fact, are continuing to change the proposed language.

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And you say it would further clarify, but I don't really see you explaining how it makes a real world difference in terms of the claim construction.

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Yes, Your Honor.

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In terms of the question regarding the changes, I know that Microsoft has raised that question as well.

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In the patent owner response, the patent owner clearly stated that we wanted to insert per datum

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as the term.

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And I guess it became fairly clear there was some confusion about whether per datum, singular or plural, it was offered up at the oral hearing that it could be changed to per dimension, which again is consistent with the language.

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And we are basically saying for the clarification, the full phrase would be per dimension of data.

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And Your Honor, I think that the clarification is because it makes clear

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that each of these functional units is supposed to instantiate one of these computational loops, and it's supposed to be performed on segments of data.

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I believe that's what the specification calls for, and it makes clear that it's segmentations of data that are being performed.

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We simply think that it adds clarity.

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Yes, but in response to Judge Pro's question, you just admitted that the board

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said that its construction included acting on a dimension of data.

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So why isn't that sufficient?

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Candidly, Your Honor, it should be sufficient.

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But when you see the way that the board applied the computational loops, and for example, with the splash 2 reference, it appears that there was some confusion.

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There was some misunderstanding that the computational loops here

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are to be acted on these dimensions of data and not simply any sort of loop.

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We would otherwise agree with Your Honor that yes, the computational loops looking up in the context of the claim are supposed to be acting on these dimensions of data.

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Well, that matters, Mr. Key.

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This is Judge Prost again, doesn't it?

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Because what you've just said sounds to me more like a substantial evidence issue if we've moved away from the matter of disagreeing on claim construction.

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So at least our standard of review is different for those two questions.

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You would agree with that, correct?

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I would agree with that, Your Honor.

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I would simply say, though, that this interpretation, both the board's, the board rested its interpretation on the language of the specification alone, which would make it de novo review.

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And we likewise are arguing that this is the plain meaning according to the claim language and the specification, which would be de novo review for the claim interpretation.

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One last question on this construction.

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I mean, why isn't this argument waived?

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I mean, you actually said to the board, we'd like you to make this change, but we're actually fine.

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We don't disagree with your preliminary interpretation.

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Why isn't that enough to say that should be the end of the issue?

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Well, Your Honor, it's not accurate that we told the board that we were fine with the construction.

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I believe you're talking about the CIDRON Appendix 981.

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And the full sentence there was the patent owner didn't disagree but felt that a clarification was necessary.

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That's where the per datum qualifier was added.

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And in fact, if you look a couple of pages later after the argument, the full argument, exposition of the argument, patent owner said that its interpretation or its construction with the per datum limitation should be adapted.

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That was not weighed.

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It became a question of, I think, whether it's per datum equivalent to a dimension of data.

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And we think that based on the representations, the arguments, and even in the board's opinion, it seems to be clear that they are a function of the equivalent purposes of this claim construction.

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So your real argument is, I'm sorry, your real argument is that the splash 2 doesn't satisfy that aspect of the claim

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the claim.

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Is that what you're saying?

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Well, that is yes, that is a that is our argument that it does not satisfy the aspect of the claim.

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In fact, as we pointed out in our briefs, we you probably could do either interpretation and you still see that splash two does not meet the elements of the claim.

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But our purpose for pursuing this claim construction again for your honor is just for purposes of clarity.

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We think this has been a consistent problem in this IPR

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that the board has introduced some lack of clarity rather than clarity.

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And we simply try and believe that our job is to get this right and make these claims clear.

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And we think that adding the over dimension of data will just make implicit what is implicit.

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Does that address your honest question?

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Yes, that's fine.

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Go on.

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I'm going to move now to the passing data seamlessly limitation.

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And there, a good part of the issue here is that the board inserted the term directly into the construction.

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The problem is, however, neither the specifications on the file history used directly to describe a connection between these computational, excuse me, functional units and computational loops.

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That was inserted by the Microsoft's expert and then adopted by the board.

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In fact, when the specification uses directly, it uses it for a completely different structure.

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It uses, if you'll look at, for example, APPX 244 in lines 5, 31 to 53, and that's the 324 pattern, and 276 lines 5, 29 to 51, you'll see that directly is used to

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discuss the connection of the chip that has all of the functional units on it to the remainder of the system.

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And by contrast, it says specifically that the functional units are to be connected by reconfigurable routing resources inside each chip.

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There's nothing to suggest there needs to be any sort of a direct connection or... What embodiment in the specification is excluded by the board's construction?

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I don't believe that there is an embodiment that is expressly excluded by the board's construction, Your Honor.

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But if you look at the figure two and the accompanying text, it's very clear, though, that there are to be intervening structures or intervening structures can be permitted between the functional units.

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And I think the board's construction directly, which they stated means that there are no intervening structures, cannot be right because according to the

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The figure two, there have to be reconfigurable resources are intervened between these functional units.

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So it is inconsistent with figure two for sure.

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And we believe that the plain language of the specification indicates that there is nothing to say that there is a connection of these functional units without any intervening structures.

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And we add to that, your honor, that Dr. Stone, Microsoft's expert, he testified that you can have an intervening structure, you can have a register, as long as it is part of the processing element.

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In other words, it's connecting these two functional units.

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So it seems very clear that the directly is doing nothing but introducing some ambiguity, and in fact,

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If you look at APPF 41, the board said that in the context of a particular written document, the construction of the term would depend on how the reference describes the processing element and the communication of data to and from the processing element.

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In other words, it's in the eye of the beholder, but that is contrary to the basic purpose of claim construction.

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It's added ambiguity, not removed.

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So our position is that

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There is no support for the adding directly into the claim.

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And in fact, it runs completely contrary to the spec and introduces ambiguity.

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With that, Your Honor, I'll reserve the remainder of my time.

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OK.

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Thank you, Mr. Key.

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Mr. Love, when you're ready.

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Thank you, Your Honor.

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Nathaniel Love for Appellee Microsoft Corporation.

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I'd like to start with the claim construction of computational loop and go to a couple of the questions that the panel asked.

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Starting with your question, Chief Judge Prost, as to what the differences between the constructions they're proposing now and what was proposed below.

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So the difference Mr. Key identified was this language over a dimension of data.

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But of course, that difference was not raised in the preliminary response in the constructions they proposed there, nor was it raised in the response.

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So if this is a critical difference, it's one that is raised far too late to provide a basis to disturb what the board did here.

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This series of clarifications that patent owner is making ultimately doesn't go anywhere different from what the board already analyzed.

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And the key issue here, if what they are proposing is a consistent sequence, somehow a consistent sequence of clarifications,

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related to this per datum idea that showed up for the first time in the patent owner response, the board addressed that argument and it found the claims unpatentable under that construction.

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But then your friend on the other side talked a lot about the word dimension, right?

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Dimension of data.

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That seemed to be introduced, not just the per datum, right?

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Correct, Your Honor.

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And that phrase did show up very late in the game at the oral hearing.

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But the board addressed that.

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The board at appendix 32 to 33 explained why including the words dimension of data was unnecessary in the construction because other claim language addresses it.

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And the idea of simply swapping dimension of data for the per datum construction is unsupported by the specification.

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So this argument was addressed by the board and the argument that was presented here simply doesn't challenge any of that analysis.

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Ultimately, patent owner is challenging a construction that the board based on a dictionary definition that patent owner itself provided in its preliminary response.

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And after seeing that construction, patent owner wrote that it did not disagree.

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And with respect to the question that Judge O'Malley asked, patent owner suggests somehow the context of their statement when they said they did not disagree made clear that they actually did disagree.

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And just now he suggested that their response said this clarification was necessary.

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That's not accurate.

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If you look at Appendix 981, they never say that this clarification was necessary.

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They simply say it's a proposal of a small clarification.

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Words matter and what they told the board was they did not disagree.

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If they thought that clarification was necessary or the construction would be legally wrong, they had an obligation to say so and to be clear about that.

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They did not, and so at this point they can't urge that this decision be vacated because the board did not adopt that clarification.

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Getting back to Judge Prost's original question to your friend on the other side, what's the practical significance of this?

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What does it mean to have to have a dimension of data limitation in the claim?

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Your Honor, I'm not sure that there is any practical significance.

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I certainly think it's a construction they've raised far too late.

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It hasn't been developed in the record because of that.

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And that's a reason to simply reject it.

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But practically speaking, the way that the prior artworks and the way the patent works, I'm not sure that it makes any difference at all.

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And that's certainly not a showing that they've made.

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And in particular, that's supported by what the board already said at appendix 32 to 33, where

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the claim construction they were attempting to change to, the board said splash two would anticipate under that construction anyway.

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So I'm not sure there is any difference at all and I think the board's analysis of the construction they proposed supports that.

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I'd also like to address the argument concerning seamlessly.

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First, the board's construction is based on the specification and in particular by citing figures two,

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and figures seven AB and eight AB of the patent.

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And Mr. T referenced figure two somehow as causing a conflict with the board's construction, but the board relied on it.

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And what's shown in figure two is a series of directly connected functional units.

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Those direct connections are what the board pointed to, including prosecution history and inventor testimony, all of which indicated that data is passed directly between loops.

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Patent owner also references this idea that Dr. Stone's testimony was somehow confusing.

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They made that argument to the board and the board addressed it and that's at a page, pages, appendix 39 to 41.

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The board explained that the testimony was not confusing and explained that there was no ambiguity or contradiction.

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Well, isn't there, as I understood, this is Judge Prouse, their alternative claim construction included communicating the data over the reconfigurable routing sources.

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And that language is in the specification, right?

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Yes, Your Honor, it is.

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It is.

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The question is whether the portions of the specification that they relied on below,

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and the portions of the specification that rely on here has somewhat been a shifting target.

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But what the final written decision explains at appendix 37 to 38 is the passages they have cited don't concern how computed data is communicated between computational loops.

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And to the extent those passages reference interconnections between functional units, that does not necessarily require that communication is limited to using particular interconnections.

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those passages of the specification don't somehow overcome the other illustrations of the specification, including the figures that show direct connections.

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In other words, your position is that interconnection is not defined as reconfigurable routing sources.

[00:19:06] Speaker 01:
It may be an example of interconnection, but it's not a definition of it?

[00:19:11] Speaker 02:
I think that's how the board viewed it, Your Honor, yes.

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The only other claim construction issue here is the third one concerning establishing a stream communication connection.

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Mr. Key didn't address it.

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We'd certainly be fine standing on the arguments as presented in our briefs as well as for the substantial evidence issues.

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So if the court has no further questions, we would ask that the final written decisions be affirmed.

[00:19:40] Speaker 01:
Hearing nothing further, thank you.

[00:19:46] Speaker 01:
Mr. Key, you have three minutes remaining.

[00:19:50] Speaker 03:
Thank you, Your Honor.

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On this issue of the computational loop and whether things were raised too late, I would invite Your Honors to, I mentioned these pages before, look at appendix 981 through 984, where the patent owner did specifically argue

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inserting at least the per datum construction and concluding with thus the board should adopt direct streams construction of this term.

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I'm not sure where the ambiguity is there, any confusion is about whether or not patent owner actually did raise a question very early in the proceedings and appropriately as to whether or not the board's construction was correct.

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And I believe it's fairly clear that patent owner said they did not believe that it was entirely accurate.

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In terms of the seamlessly limitation, I'd like to point out that the language in the specifications, and specifications I should say, that reads as follows.

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The adaptive processor includes an adaptive processor chip, incorporates a large number of functional units interconnected by reconfigurable routing resources on the same chip.

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So the point being is, there are structures that are connecting these functional units on these.

[00:21:15] Speaker 01:
Excuse me, Mr. Keyes.

[00:21:16] Speaker 01:
Sorry to interrupt.

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This is Judge Prosper.

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Seamlessly doesn't appear in the specification, correct?

[00:21:22] Speaker 03:
That is correct, Your Honor.

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Seamlessly does not appear in the specification.

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But there's a little bit of stepping back a second.

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It was known in the art to pass data from one functional unit to another in a high performance computing.

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But in that case, it was done from one chip to another across a boundary or seam.

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And when you moved all the function units onto the same chip, you no longer needed that seam.

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And we believe that that was, we presented the evidence that those of skill in the art would understand that seamlessly simply means that you are moving it without interruption and what have you.

[00:22:03] Speaker 03:
There was nothing to say that there were never any intervening structures.

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In the art, when you used these function units, there were switches and such that were connecting the functional units.

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And again, Dr. Stone said that you could insert a register between the two, another structure, and it would meet the definition.

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So the directly add to ambiguity is all it is.

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If it can be done directly, that's just a subcomponent, if you will.

[00:22:35] Speaker 03:
then adding directly simply as the ambiguity as we pointed out.

[00:22:42] Speaker 03:
And the other point I'd like to make, Your Honor, in terms of the proposal, proposed plan construction for computational loop is that all the patent owners are trying to do is just sort of clarify why the inventions are patentable over the prior art.

[00:23:01] Speaker 03:
We think it adds clarity

[00:23:03] Speaker 03:
We don't see that there's anything untoward or inappropriate about that.

[00:23:08] Speaker 03:
We think that's what we should be doing and therefore we think that the addition of the over dimension of data which is completely supported by the specification is appropriate.

[00:23:19] Speaker 01:
Thank you.

[00:23:21] Speaker 01:
We thank both sides and the case is submitted.