[00:00:01] Speaker 00: The United States Court of Appeals for the Federal Circuit is now open and in session. [00:00:05] Speaker 00: God save the United States and this honorable court. [00:00:12] Speaker 01: Good morning, everyone. [00:00:13] Speaker 01: The first awkward case this morning is number 20, 1303, Micron Technology Incorporated against North Star Innovations Incorporated. [00:00:24] Speaker 01: Ms. [00:00:24] Speaker 01: Bostrick, when you're ready. [00:00:25] Speaker 00: Thank you, Judge Newman. [00:00:29] Speaker 00: May it please the court. [00:00:31] Speaker 00: There is simply no plausible dispute that the prior Tachibana reference discloses each of the elements of the 274 patent at issue in this appeal. [00:00:42] Speaker 00: To start with claim 10, the claim requires that the differential amplifier has an output driven by an emitter or a source of a transistor. [00:00:52] Speaker 00: The 274 patent shows one transistor generating the output and providing it to another transistor, [00:00:58] Speaker 00: where it's driven through the emitter to the level conversion circuitry. [00:01:02] Speaker 00: And Tachibana has that same arrangement. [00:01:05] Speaker 00: One transistor generates the output, it provides it to transistor 131, and the output is driven through the emitter of transistor 131 to the level conversion circuitry. [00:01:16] Speaker 00: The board thought it mattered that Tachibana labels that driving transistor as part of the level converter, while the patent labels it as part of the differential amplifier. [00:01:25] Speaker 00: But it doesn't matter. [00:01:26] Speaker 00: Neither North Star nor the board has offered a basis on which to impose that requirement on claim 10. [00:01:31] Speaker 00: An unrebutted expert testimony shows that Tachibana's transistors work exactly the same as the ones in the 274 patents embodiment. [00:01:40] Speaker 01: Well, isn't there argument that if you read that limitation in light of the specification, then you already have a limitation which avoids Tachibana? [00:01:53] Speaker 00: That's their argument, your honor, but there's no support for that in the specification. [00:01:58] Speaker 00: And the board didn't identify any either. [00:02:01] Speaker 00: All that the specification gives are examples that include an element driving an output to another element, but there's absolutely nothing in the specification that suggests that that's limiting. [00:02:13] Speaker 00: On the contrary, the specification over and over states that it is describing one embodiment [00:02:20] Speaker 00: one embodiment and that alternate embodiments of the present invention can use different circuit elements. [00:02:26] Speaker 02: Ms. [00:02:26] Speaker 02: Bosswood, this is Judge Chen. [00:02:28] Speaker 02: You seem to be understanding the term driven by and claimed 10 as meaning something on the order of conveying, like an emitter of a transistor somehow conveying the differential amplifier output. [00:02:48] Speaker 02: I would think there's another way of understanding driven by, and that's something like generated by, where the emitter of the transistor as claimed is generating the differential amplifier output. [00:03:02] Speaker 02: And if you understand driven by in that way, it makes eminent sense why the emitter of the transistor would necessarily be part of [00:03:14] Speaker 02: the differential amplifier in order to generate the differential amplifier's output. [00:03:21] Speaker 02: And then when you look at the specification and the way it talks about the emitters of transistors 123 and 132 of the differential amplifier providing that output, it starts to make sense to me at least why you would think that driven bias used in claim 10 would be [00:03:45] Speaker 02: really best understood as meaning generated by, just as the emitters disclosed in the specification are generating the differential amplifier's output. [00:03:57] Speaker 02: So in that sense, can you explain what's wrong about that thinking for me? [00:04:05] Speaker 00: Certainly, Your Honor. [00:04:06] Speaker 00: The patent makes clear and the unroboted expert testimony is that the generation of the output is separate from the driving of the output and that there are different circuit elements that are performing each function. [00:04:24] Speaker 00: I think to understand this, it's very helpful to compare Figure 2 of the 274 patent, which is at Appendix 207, [00:04:32] Speaker 00: In figure 15 of Tachibana, which is among other places at page 10 of our opening brief, and to do so by reference to Dr. Baker's explanation of how these circuits work, which again is unrebutted expert testimony. [00:04:46] Speaker 00: So you have a first pair of transistors. [00:04:50] Speaker 00: In figure 2 of the 274 patent, that's transistors 127 and 131. [00:04:54] Speaker 00: And in figure 15 of Tachibana, it's transistors 126 and 127. [00:05:01] Speaker 00: those are the transistors that generate the differential output. [00:05:06] Speaker 00: And that's the output of the differential amplifier. [00:05:09] Speaker 00: What happens next is that that output goes to another transistor. [00:05:14] Speaker 00: In the 274 patent, that's transistor 123. [00:05:18] Speaker 00: And in figure 15 of Tachibana, that's transistor 131. [00:05:23] Speaker 00: And then those transistors act as emitter followers. [00:05:27] Speaker 00: This is described in the patent at the top of column 5 on appendix 210. [00:05:32] Speaker 02: Right, this is where the top of column five says transistors 123 and 132 function as emitter followers and provide the output of differential amplifier 100, right? [00:05:45] Speaker 00: That's right, and Dr. Baker's underbutted testimony is that that's also what transistor 131 is doing in Tachibana. [00:05:52] Speaker 00: It's acting as an emitter follower, taking the differential output that was generated by the other paratransistors and providing it to the circuitry that will perform the level conversion. [00:06:07] Speaker 00: And so whether you think about this as a matter of claim construction or a matter of anticipation, there's no dispute here that these two circuits are operating the same way and the board just got it wrong. [00:06:19] Speaker 00: And that's also true for claim two, right? [00:06:23] Speaker 00: Claim two in the 274 patent requires a clock delay circuit. [00:06:27] Speaker 00: And here, too, the 274 patent shows one embodiment, and Tachibana's embodiment works the same way. [00:06:33] Speaker 00: They both create delayed versions of their input signals, and they output them as clock signals that will enable and disable the differential amplifier. [00:06:43] Speaker 00: And that's what both experts agreed was the plain meaning of that claim term. [00:06:47] Speaker 02: Well, let's assume for the moment that I disagree with you that the expert of the patent owner agreed with your expert [00:06:56] Speaker 02: that clock delay circuit has a plain, well-defined meaning. [00:07:03] Speaker 02: Outside the context of this patent, I know you were emphasizing that heavily in your brief. [00:07:12] Speaker 02: What evidence do you have in the record to point to that clock delay circuit, as that term is used and claimed to, has a plain and ordinary meaning? [00:07:23] Speaker 00: So we certainly have the evidence of our expert, Dr. Baker, which is most clearly at appendix 1901. [00:07:30] Speaker 00: Right. [00:07:30] Speaker 02: I saw 1901, and it's just a very quick conclusory drive-by statement that your expert makes that, in his opinion, a circuit that is designed to delay a clock signal in some manner. [00:07:49] Speaker 02: And I guess what I'm wondering is why is that [00:07:52] Speaker 02: so clear that that's the plain, ordinary meaning, because it's not so clear to me that there was some pre-established meaning of clock delay circuit. [00:08:03] Speaker 02: It's not a term of art or anything like that, is it? [00:08:06] Speaker 00: It's not a term of art, but what it is, it's very [00:08:10] Speaker 00: simple, straightforward, and candidly broad claim language. [00:08:14] Speaker 00: And that's what North Star's expert agreed that this is as a very broad meaning. [00:08:19] Speaker 00: That's at appendix 94. [00:08:21] Speaker 02: Well, let's assume for the moment that, you know, I disagree with you that the patent owner's expert conceded to what you say he conceded to. [00:08:30] Speaker 02: So let's just focus on what you've got going for your side from your expert. [00:08:35] Speaker 02: Is this one [00:08:37] Speaker 02: this one assertion that's not backed up by anything. [00:08:41] Speaker 02: Is that right? [00:08:44] Speaker 00: It's, I mean, I think that's pretty typical when an expert is opining and it's different here only because we don't have, normally you would have something in the specification that uses the language and here of course we don't. [00:08:57] Speaker 00: There's nothing in the patent, the only time the patent uses the term clock delay circuit is in claim two. [00:09:05] Speaker 00: And so the patent seems to presume that people will know what that means. [00:09:08] Speaker 00: And I don't think it's then surprising that the expert would say, yeah, it's a circuit that delays a clock signal. [00:09:17] Speaker 00: And I'm sorry. [00:09:19] Speaker 02: Even if we were to go down this road with you and try to imagine what clock delay circuit means in some ordinary sense outside the context of the patent, why wouldn't it necessarily, why wouldn't the best guess be [00:09:35] Speaker 02: you take an actual clock signal from a clock and then you add some delay to it. [00:09:44] Speaker 02: And that's a clock delay circuit. [00:09:46] Speaker 02: That's what clock delay circuit does. [00:09:49] Speaker 00: So I agree with your honor to the extent you're saying that the meaning is add some delay to a clock signal. [00:09:55] Speaker 00: What it's important to remember is that clock signal is being used in a particular way in this patent. [00:10:01] Speaker 00: We have a construction of that term from the board that North Star does not dispute. [00:10:05] Speaker 00: This is Appendix 41. [00:10:07] Speaker 00: The board construes a clock signal as a control signal that enables or disables a circuit element. [00:10:15] Speaker 00: So that's what's required in this patent. [00:10:17] Speaker 00: That's what the timing circuit, the clock delay circuit, has to delay. [00:10:22] Speaker 00: And that's exactly what Tachi Bana showed. [00:10:25] Speaker 02: And this 274 patent, it discloses really two embodiments, one with a timing circuit and one without a timing circuit, right? [00:10:35] Speaker 00: No, the timing circuit is required by the 274 patent. [00:10:42] Speaker 00: I see him into my rebuttal. [00:10:44] Speaker 00: I'm happy to answer further questions or I'll reserve my time. [00:10:47] Speaker 01: Well, we'll see. [00:10:48] Speaker 01: Judge Jen, do you wish to pursue this point a little further? [00:10:51] Speaker 02: No, thanks. [00:10:53] Speaker 03: Let me ask one question. [00:10:55] Speaker 03: This is Judge Lynn. [00:10:56] Speaker 03: Yeah. [00:10:58] Speaker 03: The only context I can find for the meaning of clock delay circuit in the 274 patent is the description in figure two of the timing circuit. [00:11:10] Speaker 03: which is a circuit having a clock signal input from which two versions of the clock signal are output, one delayed and one are not. [00:11:19] Speaker 03: Am I missing something? [00:11:22] Speaker 00: So that is not described as a clock delay circuit, and in fact that's depicted as a timing circuit. [00:11:28] Speaker 00: If you take what the board found, the board thought that this was not the [00:11:32] Speaker 00: embodiment showing a clock delay circuit, they said that the figure two embodiment is rather the specific circuit that's claimed separately in dependent claim 13. [00:11:41] Speaker 00: And I would point your honor to column five of the specification in which with reference to figure two, it repeatedly states this is one embodiment of the present invention and that the two clock signals are not required in the present invention. [00:11:57] Speaker 03: All right. [00:11:58] Speaker 03: Fine. [00:11:58] Speaker 03: Thank you. [00:11:59] Speaker 03: That's very helpful. [00:12:01] Speaker 00: Thank you. [00:12:02] Speaker 01: Okay, now we'll save you rebuttal time and let's hear from the other side, Mr. Flynn. [00:12:09] Speaker 04: Good morning, Your Honors. [00:12:11] Speaker 04: I will start with, in reverse order of what my colleague argued, I will start with Claim 2. [00:12:18] Speaker 04: And I will start first of all with the part of the board's construction that requires that the clock delay circuit receive a clock signal. [00:12:28] Speaker 04: And I agree [00:12:30] Speaker 04: I believe it was you Judge Chen who was suggesting the clock delay circuit is not some term of art or that would have by itself a plain and ordinary meaning. [00:12:43] Speaker 04: And it is therefore necessary to resort to the specification for a person of ordinary skill to have understood what that term clock delay circuit means. [00:12:54] Speaker 04: To the extent that anything can be gleaned from the claim language itself though, [00:12:59] Speaker 04: a clock delay circuit suggests that it is a circuit. [00:13:03] Speaker 04: And I don't think that this is disputed by my colleague. [00:13:07] Speaker 04: It is a circuit that delays a clock, meaning that a clock has to be input into it. [00:13:13] Speaker 04: It's not a clock generation circuit that simply generates a clock signal. [00:13:20] Speaker 04: It is a clock delay circuit, meaning that it delays a clock signal. [00:13:24] Speaker 04: And you can't delay a clock signal unless it is a clock signal that is input into the circuit. [00:13:30] Speaker 04: The specification confirms that that's what was meant by clock delay circuit, that a clock delay circuit has to receive a clock signal as an input. [00:13:41] Speaker 04: And the board correctly found, this is at page 42 of its final written decision, that the parties did agree that clock delay circuit receives a clock signal as an input. [00:13:51] Speaker 04: And they agreed by, just as North Star suggests is necessary, by looking to the specification. [00:13:58] Speaker 04: And so, for example, in the petition, this is appendix page 266, Micron acknowledged that although the patent does not define clock delay circuit, the only embodiment of a clock delay circuit described in the specification has a clock signal as an input. [00:14:19] Speaker 04: And Micron's expert, Dr. Baker, in support of that petition, said the same thing. [00:14:26] Speaker 04: He also said, Dr. Baker, [00:14:28] Speaker 04: that this is in his declaration that appendix 1023, that like the 274 patent, Tasha Bonnet generates clock signals by passing them, meaning the clock signals, through inverters and other intervening logic. [00:14:46] Speaker 04: And then he came back in his reply declaration, although he was now advocating a broader construction. [00:14:54] Speaker 04: But even in his reply declaration, he makes crystal clear [00:14:58] Speaker 04: in his opinion that a clock delay circuit is a circuit designed to delay a clock signal. [00:15:05] Speaker 04: The only way you can be designed to delay a clock signal is if the clock signal is input to it. [00:15:11] Speaker 04: So now that's the first part of the board's construction as to whether or not the clock delay circuit has to receive a clock as an input. [00:15:21] Speaker 04: As to the portion of the construction that requires two different versions, [00:15:26] Speaker 04: with one version, two different versions of the input signal, with one version delayed compared to the other version. [00:15:35] Speaker 04: The board's construction does not, as Micron would argue, limit the clock delay circuit to the specific embodiment described in Figure 2 of the specification. [00:15:46] Speaker 04: To the contrary, the board rejected North Star's proposed construction that construed clock delay circuit to [00:15:54] Speaker 04: not only provide two different versions of the input, but also to provide the particular delay that is described in Figure 2. [00:16:03] Speaker 04: The board said that was limited to the specific embodiment of Figure 2 and improperly limits the scope of the claim. [00:16:12] Speaker 04: But that doesn't mean that you abandon the specification altogether, and the board did not abandon the specification altogether. [00:16:19] Speaker 04: Under Phillips, you never abandon the specification. [00:16:22] Speaker 04: And in looking to the entirety of the specification, the board said, understanding how the circuit works and understanding the purpose of the invention, that although it doesn't have to be delayed precisely in the way shown in Figure 2, the output of the clock delay circuit does have to be two different versions of the input that are in some way delayed compared to one another. [00:16:47] Speaker 04: And contrary to Micron's argument, the board did provide [00:16:51] Speaker 04: affirmative rationale in support of that construction. [00:16:55] Speaker 04: It pointed to the specification that talks specifically about the advantages and the need for the different versions, one delayed with one another. [00:17:09] Speaker 04: It is specifically by that kind of an output that the circuit selectively enables and disables the differential amplifier and the level converter. [00:17:20] Speaker 04: That was explained by Dr. Cotry and that testimony was unrebutted. [00:17:24] Speaker 04: It is that kind of output that allows the selective enablement of the circuit components that allows a reduction in power consumption and allows increased speed. [00:17:37] Speaker 04: And the board understood that output of these two different versions of the input that are delayed in some way, it avoids the timing relationship problems [00:17:47] Speaker 04: that result from or can result from variations in manufacturing processes and temperatures and power supply voltage. [00:17:56] Speaker 02: Now, if I talk... Councilman Jess Chen, just getting to that point, my understanding of reading this patent disclosure was the purpose of this patented invention is to avoid the problems of using two separate clocks and using just a single clock, but then providing circuitry that can produce [00:18:18] Speaker 02: two different clock signals that are different versions of each other from that single clock to overcome the problems of using two clocks. [00:18:28] Speaker 02: Is that right? [00:18:30] Speaker 04: Yes, that's exactly right. [00:18:31] Speaker 04: When we're talking about the timing relationship, the advantage of being able to use a single clock as an input into the circuit that then outputs two versions of that clock [00:18:41] Speaker 04: That avoids the timing relationship problems that would result if you were using separate clocks to time the system. [00:18:50] Speaker 02: Your opposing council raised the question about how to understand clock delay circuit based on how the board construed clock signal, which is, I think, something to do with some kind of control signal that enables, disables either a differential amplifier or a [00:19:11] Speaker 02: level converter, and in your disclosure, the clock signal 78 that's getting inputted into your disclosed timing circuit is not the actual control signal that's enabling or disabling the differential amplifier level converter in that disclosed embodiment. [00:19:35] Speaker 02: So is there an inconsistency there between how the board can street clock signal and [00:19:41] Speaker 02: how that lines up with your disclosure? [00:19:44] Speaker 04: No, Your Honor, because the output of the clock delay circuit in the 274 patent are versions, are two different versions of that same clock signal. [00:19:55] Speaker 04: So 78, clock 78 goes in and what comes out are just two different versions of that same clock. [00:20:01] Speaker 04: They are both inverted and one of them is delayed from the other. [00:20:06] Speaker 04: But they are both versions of that clock 78. [00:20:09] Speaker 04: They are not entirely new signals from clock 78. [00:20:15] Speaker 04: So it is not inconsistent. [00:20:17] Speaker 04: It is the versions of clock 78 that selectively enable and disable the differential amplifier and the level converter. [00:20:27] Speaker 04: Now, Ms. [00:20:28] Speaker 04: Boswick had also suggested [00:20:30] Speaker 04: at least in their brief, and I suggest, I suspect that I will hear about this somewhat in rebuttal, that it was the purpose of the clock-free latch as stated in the 274 patent to avoid these timing relationship problems. [00:20:45] Speaker 04: And it is true that the clock-free latch, which also obviates the need for separate clocks to clock the latch, helped to avoid those timing relationship problems. [00:20:57] Speaker 04: And that is described as one of the advantages of the 274 pattern. [00:21:01] Speaker 04: But it's not the only advantage. [00:21:03] Speaker 04: It's not the only purpose. [00:21:04] Speaker 04: And it's not the only thing that avoids those timing relationship problems. [00:21:10] Speaker 04: Having two different versions of the input clock signal to selectively enable and disable the circuit elements, that too adds to the advantage of being able to avoid the timing relationship problems. [00:21:24] Speaker 04: And all of the advantages that the board pointed to in its decision are directly from the patent. [00:21:32] Speaker 04: So the specification does indeed explain that all of these advantages of avoiding timing relationship problems, increasing speed, reducing power consumption, that was all spelled out in the specification and specifically tied into the clock delay circuit limitation. [00:21:53] Speaker 02: Could you get to claim 10 and the driven by limitation? [00:21:58] Speaker 04: Yes. [00:22:01] Speaker 04: In claim 10, it is correct that the claim 10 of the 274 patent is talking about a signal that is driven by is a signal that is generated by. [00:22:18] Speaker 04: It is not simply passing through. [00:22:21] Speaker 04: It's not simply conveying. [00:22:22] Speaker 04: And that's what Micron has described the bipolar transistor 131 to do, simply to receive the output of the differential amplifier in Tashibana and to pass it on to the level converter in Tashibana. [00:22:38] Speaker 04: But the 274 pattern makes clear that that driving transistor, first of all, has to be within the differential amplifier. [00:22:49] Speaker 02: Your emitter followers, 123 and 132 in your spec, are they generating anything? [00:22:56] Speaker 02: Are they driving anything? [00:22:58] Speaker 04: They are. [00:22:59] Speaker 04: If you will see in Figure 2, there is the relationship as shown in that Figure 2, 123 and 132, 127 and 131. [00:23:05] Speaker 04: So to the extent that there is disclosure in the 274 specification, those transistors are working together to ultimately provide the output [00:23:18] Speaker 04: of the differential amplifier to the level converter. [00:23:21] Speaker 04: And it is shown in Figure 2 and described in the 274 specification that it is the emitter of bipolar transistors 123 and 132 that drive those outputs to the level converter. [00:23:35] Speaker 03: Mr. Flynn? [00:23:36] Speaker 03: Yes. [00:23:37] Speaker 03: This is Judge Lynn. [00:23:39] Speaker 03: Does the emitter [00:23:42] Speaker 03: Does transistor 131 of Tachibana function as an emitter follower in the same sense? [00:23:50] Speaker 04: It acts and is described as an emitter follower. [00:23:54] Speaker 04: But what is not described in Tachibana is that it be part of the differential amplifier. [00:24:01] Speaker 04: In fact, Tachibana expressly discloses that it is part of the level converter. [00:24:07] Speaker 03: And I respect that. [00:24:08] Speaker 03: Those are just labels. [00:24:09] Speaker 03: I mean, isn't it more important that we focus on how these components function in assessing whether the claim language is met? [00:24:20] Speaker 04: Well, to some extent, you look at how the circuit functions. [00:24:23] Speaker 04: But you also do have to look at how the prior ARC reference, the 102 reference that they're relying on for anticipation, how it discloses those elements. [00:24:33] Speaker 04: You know, because they have to rely on the four corners of the prior art reference document to anticipate. [00:24:40] Speaker 04: And so it is important to understand how Tashibana discloses what they say is the element that meets the claim limitation. [00:24:48] Speaker 04: And Tashibana clearly says that it's not part of the differential amplifier. [00:24:52] Speaker 04: Moreover, there's not really much disclosure in Tashibana as to what bipolar transistor 131 does other than to convey [00:25:02] Speaker 04: the output to the level converter or to receive the output of the differential amplifier and convey it to the rest of the level converter. [00:25:10] Speaker 04: There's not the same kind of disclosure in Tashibana as there is in 274 as to how transistors 123 and 132 work together with 127 and 131. [00:25:22] Speaker 04: So without that kind of disclosure, it is a micron burden to prove the anticipation. [00:25:26] Speaker 04: Without that kind of disclosure, [00:25:28] Speaker 04: They can't meet that burden, and particularly so when Tasha Bonner describes it as being part of a level converter rather than the differential amplifier. [00:25:36] Speaker 01: Well, let me just ask a quick question relative to this point. [00:25:40] Speaker 01: Because what seems to be the problem is that we have claim limitations which on their face seem to be stated quite broadly until you go through the specification and the details and the kind of discussion we're having here and decide, no, it really needs to be limited because. [00:26:03] Speaker 01: And then we have the prior art, we have the disclosure and so on. [00:26:07] Speaker 01: Was there any proposal during this procedure to amend the claims to limit the definition of these two limitations and claims to intend to include the limitations that the board gave to them? [00:26:30] Speaker 04: No, Your Honor. [00:26:30] Speaker 04: There was no attempt to amend any of the claims. [00:26:34] Speaker 04: And again, I think that the board recognized that [00:26:37] Speaker 04: the claim language in both 2 and 10, the way that the board construed those claim limitations was adequately supported by the disclosure of the specification. [00:26:49] Speaker 04: And with respect to the driven by, particularly, the board looked to all the different various aspects of the 274 specification that revealed what the patentee meant, what they talked about driving by or driven by. [00:27:04] Speaker 04: and revealed various, disclosed various circuit elements where one drove the output of that element to another element, and the driving component was always located. [00:27:16] Speaker 04: So, and again, as we argued in our brief, in their brief, or initially in their petition, they altered the disclosure of Toshibana to show bipolar transistor 131 within the differential amplifier. [00:27:31] Speaker 04: And that could have only been as an acknowledgement that under the claim as properly construed, that driving transistor had to be part of the differential amplifier. [00:27:40] Speaker 01: Okay. [00:27:41] Speaker 01: Thank you. [00:27:41] Speaker 01: I know that you have a cross appeal that we haven't gotten to. [00:27:45] Speaker 01: For the cross appeal, will you then rest on the briefs? [00:27:51] Speaker 04: Yes, Your Honor. [00:27:52] Speaker 04: We will rest on the briefs for the cross appeal. [00:27:54] Speaker 01: Okay. [00:27:55] Speaker 01: All right. [00:27:55] Speaker 01: Then let's, for rebuttal, let's hear from Ms. [00:27:58] Speaker 00: Bostwick. [00:28:00] Speaker 00: Thank you, Your Honor. [00:28:01] Speaker 00: I want to focus on claim two. [00:28:03] Speaker 00: We continue to believe that the board's construction was wrong. [00:28:07] Speaker 00: The arguments are in the briefs. [00:28:09] Speaker 00: But if the court agrees with the board's construction, then there's still no substantial evidentiary support for its finding of no anticipation by Tachibana. [00:28:20] Speaker 00: I want to take the two parts of the board's construction, first the input, then the output. [00:28:25] Speaker 00: the input has to be a clock signal. [00:28:27] Speaker 00: And again, I want to remind the court that the board's unchallenged construction of a clock signal in this patent is a control signal that enables or disables a circuit element such as the differential amplifier. [00:28:38] Speaker 00: At Judge 10, you pointed to clock 78 in Figure 2, and that's exactly the right place to focus because Tachibana's input signals to the timing circuit are as much a clock signal as the input in the 274 patents embodiment. [00:28:52] Speaker 00: Figure two, clock signal 78 does not itself directly enable or disable the differential amplifier or anything else. [00:29:00] Speaker 00: It gets processed through the inverters, and in the case of the second version of it, a NAND gate, before it goes on to do so. [00:29:07] Speaker 00: In figures eight and nine of Tachibana, which are the timing circuit, the inputs are combinations of address signals and others. [00:29:17] Speaker 00: It is undisputed that all [00:29:20] Speaker 00: that those signals are doing is to become the signals that will enable and disable Tachibana's differential amplifier. [00:29:26] Speaker 00: Just like in the 274 patent, those signals get processed through logic gates before they do that. [00:29:32] Speaker 00: But the board cited no basis for finding that the patent's input signal is a clock signal and Tachibana's aren't, other than the labels given to those signals. [00:29:40] Speaker 00: The fact that they get manipulated through different logic gates, it happens in both just the same. [00:29:46] Speaker 00: And Mr. Flynn has no basis for saying, well, it's the same signal in figure two of the 274 patent, and it's a different signal in Tachibana. [00:29:56] Speaker 00: As to the output, [00:29:57] Speaker 00: that the two clock signal outputs are delayed with respect to one another. [00:30:02] Speaker 00: The board found, and it is undisputed, that the outputs of Tachibana's timing circuits, including signals 19 and 21, are clock signals. [00:30:10] Speaker 00: That's at Appendix 50. [00:30:12] Speaker 00: The board also found that clock signals 19 and 21 in Tachibana are delayed with respect to one another. [00:30:20] Speaker 00: It then says, without citation, that this doesn't make them different versions of each other, but again, [00:30:25] Speaker 00: They don't have to be different versions of each other. [00:30:27] Speaker 00: They have to be delayed with respect to one another under the board's construction. [00:30:31] Speaker 02: Well, what if I understand the board's construction as delayed versions, delayed different versions of the same input signal? [00:30:42] Speaker 05: So they are. [00:30:43] Speaker 02: Tachibana teaches that, the same input signal. [00:30:47] Speaker 02: Now Tachibana is outputting two signals that will be used as clock signals in which they are [00:30:55] Speaker 02: those two output signals are both a different version of the same input signal? [00:31:01] Speaker 00: If you're talking about the exact same signal, no. [00:31:05] Speaker 00: But that's not required by the board's construction. [00:31:07] Speaker 00: And there's no basis for imposing that limitation. [00:31:11] Speaker 00: At this point, we are purely talking about an embodiment that the 274 patent specification repeatedly says is not required in the present invention. [00:31:22] Speaker 00: But even within that world, the clock signal outputs of Tachibana's timing circuit are all combinations of the same group of input signals, again, whose only function is to be used to create these output clock signals, and they are delayed with respect to one another. [00:31:41] Speaker 01: Okay, any more questions from the panel? [00:31:47] Speaker 03: No, thank you. [00:31:49] Speaker 03: No, thank you. [00:31:50] Speaker 01: Oh, okay. [00:31:51] Speaker 01: All right. [00:31:52] Speaker 01: Thanks to counsel. [00:31:53] Speaker 01: The case is taken under submission. [00:31:56] Speaker 03: Thank you, Your Honor.