[00:00:12] Speaker 03:
Thank you, Your Honor.

[00:00:13] Speaker 03:
It's Kevon Maruzzi for Appellant Monterey Research, and may please the Court.

[00:00:19] Speaker 04:
So could I just clarify one thing before you get started?

[00:00:23] Speaker 04:
If I understand correctly, the substantially oblong issue affects all of the claims of the issue, but the single local interconnect only affects a subset.

[00:00:34] Speaker 04:
Is that right?

[00:00:35] Speaker 03:
That's correct, Your Honor.

[00:00:38] Speaker 03:
And it was my intention to start with a single local interconnect layer issue.

[00:00:43] Speaker 03:
But if the court would like me to do it differently.

[00:00:46] Speaker 03:
No, no, no.

[00:00:46] Speaker 03:
Go ahead.

[00:00:47] Speaker 03:
Thank you.

[00:00:47] Speaker 03:
Your Honors, with respect to the single local interconnect layer issue, the board's error was an error of law in terms of claim construction.

[00:00:57] Speaker 03:
The prosecution history.

[00:00:59] Speaker 03:
evidences that the patentee expressly amended the claims during the re-examination in front of three examiners to exclude the design of Osada, in particular, that specific reference.

[00:01:12] Speaker 03:
And yet the board found that the proper construction of the claim should be such that it would encompass Osada's design.

[00:01:20] Speaker 03:
There has never been, to my knowledge, a case from this court that has accepted a construction

[00:01:27] Speaker 03:
that encompasses the same priority that the patentee expressly amended the claims to overcome, and that examiners acknowledge the amendment to overcome.

[00:01:37] Speaker 04:
I'm not sure that's the right approach.

[00:01:40] Speaker 04:
Just to be clear about it, without the prosecution history, the board's construction would be correct, right?

[00:01:46] Speaker 03:
And not necessarily, Your Honor.

[00:01:48] Speaker 03:
Yes, thank you, Your Honor.

[00:01:51] Speaker 03:
So this is not the case that the appellee represents where nothing in the claim language supports the construction that Monterey is seeking and that we have to look entirely beyond the claim language.

[00:02:05] Speaker 03:
The claim language, the relevant

[00:02:06] Speaker 03:
key language that the board overlooked and failed to reflect to in its construction is the following.

[00:02:13] Speaker 03:
A single local interconnect layer, the board addressed that part, but comprising local interconnects corresponding to bit lines and a global word line.

[00:02:23] Speaker 03:
And it's really that part of the claim limitation comprising local interconnects, the significance of local as modifying interconnects and limiting interconnects, as well as the fact that the local interconnects have to correspond to bit lines and a global word line.

[00:02:40] Speaker 03:
And the point of dispute and the failing on the part of the board here is to give effect to that language in the claim limitation based on the prosecution history and what the prosecution history tells us about what that language means.

[00:02:55] Speaker 03:
And effectively, the board said, when I look at the prosecution history,

[00:03:00] Speaker 03:
I don't really get it to sort of summarize the board's position that they said, I don't understand what it is about this prosecution history that you think makes your claim any different than OSADA.

[00:03:11] Speaker 03:
Well, we find that addressed by AMD's own statements in its petition, where AMD clearly did understand what the prosecution history evidence is and how it narrows.

[00:03:24] Speaker 04:
OK, but that really doesn't help that much.

[00:03:28] Speaker 04:
under personalized media in these other cases, we had to look at what was said during the prosecution to see whether it's inconsistent or consistent with one construction or the other.

[00:03:38] Speaker 04:
And I guess I'm struck by the statement that appears in J.A.

[00:03:45] Speaker 04:
1260.

[00:03:56] Speaker 03:
your construction, but not with the board's construction.

[00:03:59] Speaker 03:
That's exactly right, Your Honor.

[00:04:01] Speaker 03:
And that statement at appendix 1262, as well as a similar further explanatory comment at 1267, is exactly what AMD itself cited when it gave an interpretation of the prosecution history that's consistent with our construction.

[00:04:17] Speaker 03:
So I agree, of course, that the analysis has to be based on what was in the prosecution history.

[00:04:22] Speaker 03:
But one component of a prosecution history analysis is,

[00:04:26] Speaker 03:
Does the prosecution history evidence a sufficiently clear understanding that those of skill and the art would have taken the meaning that the patentee is asking for in its claim construction?

[00:04:37] Speaker 03:
And here we have that evidence because AMD took away the same understanding of the prosecution history that we've argued for.

[00:04:44] Speaker 02:
Let's just assume for the moment that was just a litigation position.

[00:04:47] Speaker 02:
that AMD took in a paper to figure out a way to match up its preferred prior art to the claims.

[00:04:55] Speaker 02:
But in the end, if we're going to really figure out to what degree there was prosecution disclaimer, we have to look at the prosecution history itself.

[00:05:03] Speaker 02:
And that's what matters and what you said.

[00:05:05] Speaker 02:
And exactly how the examiner did or did not map

[00:05:10] Speaker 02:
the claim to the prior art, that's I guess one component, but prosecution disclaimer comes down to what you said in the prosecution and then what we take away from those statements.

[00:05:24] Speaker 02:
So let's start there.

[00:05:26] Speaker 02:
Where in the prosecution history, what is the quotable quote from there?

[00:05:33] Speaker 02:
that the applicant said that tells us how to understand this term, single interconnected.

[00:05:40] Speaker 03:
Yes, your honor.

[00:05:41] Speaker 03:
So I want to walk through the prosecution history statements, but just as a prelude, the case law from this court also gives emphasis to the fact that the examiner evidence

[00:05:53] Speaker 03:
the same understanding, a common understanding with the applicant, and that that is reflected, for example, in a notice of allowance.

[00:06:00] Speaker 03:
And we have those further facts here as well, which we think are helpful to establishing that there was a prosecution history clarification of the scope of the claims.

[00:06:13] Speaker 03:
Now, it does not need to rise to the level of disclaimer.

[00:06:16] Speaker 03:
We think it does.

[00:06:17] Speaker 03:
But personalized media, for example, tells us it has to be clear.

[00:06:22] Speaker 03:
Has to be clear.

[00:06:23] Speaker 04:
I don't think the fact that they distinguish something really is conclusive at all.

[00:06:29] Speaker 04:
I mean, you have Ryan versus John here on the right pages of the lion.

[00:06:34] Speaker 04:
The Supreme Court says the examiner allowed something which there was no basis for an argument that was distinct from the patent convention.

[00:06:50] Speaker 04:
But go ahead.

[00:06:51] Speaker 03:
Yes, Your Honor.

[00:06:54] Speaker 03:
Judge Dyke, I want to fully agree with you in the sense that the mere fact that we said we are different than Osada during prosecution, that itself is not the claim construction.

[00:07:08] Speaker 03:
So of course that appendix 1262 I think is is one of the key starting points where the patentee explained that under the

[00:07:26] Speaker 03:
amended claim language, all the runs for the bit lines VCC, VSS, and the word line are provided in the single layer of figure three of the patent.

[00:07:37] Speaker 01:
And in other, for example... I guess that seems to me the sentence of greatest interest.

[00:07:47] Speaker 01:
It doesn't say that under the amended language all runs for bit lines are in a single layer.

[00:07:59] Speaker 01:
It says something about figure three, not about the meaning of the new language.

[00:08:07] Speaker 01:
I guess I'd like you to help me understand whether what I just said A is right and B matters.

[00:08:15] Speaker 03:
Yes, Your Honor.

[00:08:16] Speaker 03:
So I think that's an important point.

[00:08:18] Speaker 03:
The prosecution history in that section in 1262 was discussing Figure 3.

[00:08:26] Speaker 03:
But in 1268, for instance, the patentee makes it clear that they are effectively reciting the design of Figure 3

[00:08:39] Speaker 03:
for purposes of the claim amendment.

[00:08:41] Speaker 03:
And there are other citations.

[00:08:43] Speaker 01:
I'm sorry.

[00:08:44] Speaker 01:
You said 1268?

[00:08:45] Speaker 03:
1268, Your Honor.

[00:08:47] Speaker 03:
Let me turn this so I can go back into the language.

[00:08:52] Speaker 03:
So for example, 1268 provides the exemplary support for the claim changes.

[00:08:58] Speaker 03:
And it cites to figure three repeatedly.

[00:09:03] Speaker 03:
1262 itself.

[00:09:16] Speaker 04:
whether it supports your construction or the board's construction.

[00:09:23] Speaker 03:
Actually, I think it is clear from figure three and and helpfully the board appears to have acknowledged that figure three is consistent with the construction we see from its teachings at appendix 87 the board made the finding that in figure three the local interconnects for the bit lines and word line laterally displaced the relevant components all within that single layer of figure three and

[00:09:50] Speaker 03:
I'm sorry, does that address the question, or would you like me to expand on that?

[00:09:55] Speaker 02:
But the board also went further by pointing out that maybe it can be routed horizontally, but it's not required.

[00:10:07] Speaker 02:
There's nothing in the specter claims that requires such a routing arrangement.

[00:10:14] Speaker 02:
I'm looking at 87 and then back to 65.

[00:10:18] Speaker 03:
Yes, your honor.

[00:10:19] Speaker 03:
So I think this is where the board effectively took the view that although figure three is an embodiment disclosed to the patent, and although that embodiment teaches what we are seeking for the claim construction, that the specification itself and the claims, according to the board, do not limit the invention to the design of figure three.

[00:10:41] Speaker 03:
And our point is, well, that's what happened in the prosecution history.

[00:10:45] Speaker 04:
So where does the board say that figure three

[00:10:48] Speaker 04:
is an embodiment that shows the connections of all of you in a single item.

[00:11:01] Speaker 03:
Appendix 87, Your Honor.

[00:11:03] Speaker 03:
And then I would like to come back to Appendix 1262 and the connection between figure three and the claims, if I could.

[00:11:10] Speaker 01:
This is the sentence about eight lines down.

[00:11:13] Speaker 01:
Thus, although the embodiment shown in figure three illustrates routing bit line and word line signals along an interconnect layer to connect laterally displaced, either the spec or the claims require that.

[00:11:25] Speaker 01:
Is that the sentence here?

[00:11:27] Speaker 03:
Yes, Your Honor.

[00:11:29] Speaker 01:
And that might be enough for it to supply the written description support in that table on 1268 without limiting the new claim language to that.

[00:11:45] Speaker 03:
So in our briefing, in our opening brief, we make this connection between the intent of the patentee in terms of the amendment and the limitation to the embodiment of figure three.

[00:11:59] Speaker 03:
And that happens in multiple parts of the prosecution history that we have.

[00:12:03] Speaker 03:
outlined in our opening brief.

[00:12:05] Speaker 03:
But if you look at 1262 itself, the discussion with respect to Civil Key there is in the context of summarizing the conversation between the applicant and the examiners with respect to further amendments.

[00:12:20] Speaker 03:
And the summary states that the patentee explained to the examiners, we are trying to get the embodiment of Figure 3 for this claim limitation.

[00:12:31] Speaker 03:
And here's how the embodiment of Figure 3 works.

[00:12:33] Speaker 03:
And here's why that is different than OSADA.

[00:12:35] Speaker 03:
So the connection between Figure 3 and the claim limitation is one-to-one.

[00:12:41] Speaker 03:
It's not simply one way of practicing the limitation.

[00:12:45] Speaker 03:
It is the way of the limitation.

[00:12:53] Speaker 02:
At the bottom of A65, I think the board said it more clearly, where it said at the very last sentence, thus, although figure three shows bit-line signals can be routed horizontally and the global word-line signal can be routed vertically, neither the spec nor the claims require such routing.

[00:13:13] Speaker 02:
So maybe the configuration illustrated in figure three, one could imagine a scenario where you could have the connections laterally displaced.

[00:13:24] Speaker 02:
But that figure three configuration could also create a scenario where there is no lateral displacement at all.

[00:13:32] Speaker 02:
And I think that's the point the board was making.

[00:13:35] Speaker 02:
And finally, there's nothing in the claims.

[00:13:37] Speaker 02:
And then when you go look at the prosecution history,

[00:13:41] Speaker 02:
We don't see language like routing along the layer or laterally displaced interconnections or any of that kind of language that you want us to inject into the claim construction now.

[00:13:58] Speaker 03:
Your Honor, I'd like to address that at a couple of levels.

[00:14:03] Speaker 03:
First of all, the statement with respect to what Figure 3 itself teaches, I think, is further clarified at Appendix 87, where the board removes this sort of canned language and says, Figure 3 does, in fact, show the lateral displacement routing.

[00:14:18] Speaker 03:
But really, the central premise of the board's decision is to come back to the point that the specification is not limiting with respect to Figure 3.

[00:14:26] Speaker 03:
And that's certainly true.

[00:14:28] Speaker 03:
And the board then says the claims are not limiting with respect to figure three and that's incorrect because the claim language recites this local interconnect.

[00:14:37] Speaker 03:
Local interconnects comprising connections for the bit lines and the word line and the meaning of that language that is in the claim

[00:14:45] Speaker 03:
that is limiting is evidenced by the prosecution history and restricted to the embodiment of figure three.

[00:14:51] Speaker 03:
And the associated teachings for that embodiment that are in column 13 of the patent as well, and that teach this design.

[00:14:59] Speaker 04:
And that it's in all or all the work on connections with the other layer

[00:15:05] Speaker 03:
In Oh exactly as an Osada there is lateral displacement in one layer in the first layer for the word line But not for the bit line for none of them for For the word lines, but not the bit line correct and then the the lateral displacement for the bit lines are in a second layer and in fact

[00:15:23] Speaker 03:
Yes.

[00:15:24] Speaker 03:
And AMD itself explained this with respect to OSADA at appendix 183 with a very helpful diagram.

[00:15:31] Speaker 03:
And it's the same design for O. And in fact, the board found that O and OSADA are substantially the same.

[00:15:38] Speaker 03:
Your Honors, I'd like to reserve my time for rebuttal, unless you would like me to also address substantially up long.

[00:15:47] Speaker 04:
Thank you.

[00:15:47] Speaker 04:
We'll give you two minutes.

[00:15:49] Speaker 04:
Thank you.

[00:16:26] Speaker 00:
Good morning, your honors.

[00:16:30] Speaker 00:
Reece Lin, Teresa Lin for Appellee STMicroelectronics.

[00:16:35] Speaker 00:
May it please the court?

[00:16:36] Speaker 00:
The board's construction of the single local interconnect layer term was fully supported by the claim language and the specification.

[00:16:45] Speaker 00:
There's no support for Monterey's construction on the face of the patent and the sole basis for Monterey's appeal in this

[00:16:52] Speaker 00:
on this term is the prosecution history.

[00:16:55] Speaker 00:
The only dispute here is whether reversal is warranted when not a single statement in the prosecution history, either explicitly or implicitly, supports limiting the claimed interconnect layer to one where the local interconnects are routing signals laterally along the layer to connect laterally displaced contacts.

[00:17:16] Speaker 04:
So do you agree that figure three is an embodiment

[00:17:22] Speaker 04:
that is consistent with that patentee's construction but not the board's?

[00:17:30] Speaker 00:
No, I disagree, Your Honor, because if you take a look at figure three of the 805 patent, which is referred to on page 28 of the red brief,

[00:17:44] Speaker 00:
You can see that the bit line interconnects are in blue.

[00:17:53] Speaker 00:
So that's elements 38 and 39.

[00:17:59] Speaker 00:
Where the contacts are on the lower levels connecting to those interconnects are those dotted squares or dotted structures.

[00:18:09] Speaker 00:
And there are no contacts for the upper layer bit line.

[00:18:14] Speaker 00:
So as the board noted, there is no second contact to show that there would actually be routing along that interconnect to connect to contacts.

[00:18:26] Speaker 00:
and as Monterey in its below.

[00:18:30] Speaker 04:
Let me put it this way because I'm having a little difficulty following.

[00:18:34] Speaker 04:
Is it true that in figure three all the local interconnects are on a single layer?

[00:18:42] Speaker 00:
Yes, that's right.

[00:18:44] Speaker 04:
So that would seem to be consistent with

[00:18:51] Speaker 04:
It's consistent with Monterey's construction in that there are interconnects on the same layer.

[00:19:14] Speaker 00:
But it's not consistent with this requirement that there would be rounding of the signals along the layer.

[00:19:20] Speaker 04:
Well, right.

[00:19:20] Speaker 04:
Construing the patent is not going to be limited to Figure 3.

[00:19:24] Speaker 04:
But what they're ordering, as I understand it, the prosecution history, they're telling the PTO that Figure 3 is the only embodiment of the patent.

[00:19:36] Speaker 00:
I would disagree with that interpretation of the prosecution history, Your Honor.

[00:19:41] Speaker 04:
If we can... Well, that's a different question, though.

[00:19:44] Speaker 04:
But if that... If they... Once they sit in the prosecution history, the only thing that's covered by this claim is Figure 3, then they would be correct as to their claim construction, no?

[00:19:57] Speaker 00:
I would still disagree, Your Honor, because Figure 3 doesn't show lateral routing along the interconnects.

[00:20:03] Speaker 00:
It shows a single layer, and that is what's reflected in the claim language.

[00:20:07] Speaker 00:
But it doesn't show lateral routing, which is what Monterey's construction requires.

[00:20:15] Speaker 01:
confused.

[00:20:16] Speaker 01:
I guess I, and I think you understand something about the words you're using that I don't.

[00:20:23] Speaker 01:
I hear you saying diametrically opposite things about whether figure three shows lateral routing or not.

[00:20:30] Speaker 01:
And maybe that's different from interconnects not being in the same layer or I guess I had understood those to be the same thing that the internet the interconnect for the relevant things the bit lines and a word line.

[00:20:47] Speaker 01:
in their interpretation, their claim construction, that those interconnects are entirely in this layer.

[00:20:56] Speaker 01:
And now I don't understand whether you think that figure three shows that or doesn't show that.

[00:21:02] Speaker 00:
Let me try to explain, Your Honor.

[00:21:05] Speaker 00:
I think those are two separate things.

[00:21:08] Speaker 00:
The interconnects being in the layer means the interconnects are located on the layer.

[00:21:14] Speaker 01:
Are interconnects little metal channels along which signals flow?

[00:21:21] Speaker 00:
Yes, that's right.

[00:21:22] Speaker 01:
So there are little metal channels along which signals flow between the things specified in this limitation.

[00:21:30] Speaker 00:
That's right.

[00:21:31] Speaker 01:
And they're in the layer.

[00:21:32] Speaker 00:
And there are bit line and word line interconnects on that layer, both the blue and the green here.

[00:21:39] Speaker 00:
So they're both on that single layer.

[00:21:42] Speaker 00:
Now the lateral routing aspect of it means that the signals, what Monterey is saying is that the signals must route laterally along the layer.

[00:21:53] Speaker 00:
interconnects can also connect vertically through the layers.

[00:21:58] Speaker 00:
So from the lower layers through the interconnect up to the upper layers.

[00:22:04] Speaker 00:
And that's also an interconnect.

[00:22:05] Speaker 00:
So you can have interconnects on the same layer.

[00:22:08] Speaker 00:
Some of those interconnects could be routing vertically through the layers, while other interconnects may connect laterally.

[00:22:17] Speaker 01:
What I'm hearing you say, just correct me,

[00:22:19] Speaker 01:
I keep hearing you now say that the interconnects are the endpoints of

[00:22:25] Speaker 01:
of a signal path and the signal path itself can be vertical or entirely horizontal, lateral, or can include a vertical component.

[00:22:38] Speaker 01:
But I thought you had earlier said, when I asked you about the little metal channels, that those in figure three lie on this layer in figure three.

[00:22:52] Speaker 00:
Let me refer to the definition of a local interconnect.

[00:22:56] Speaker 00:
Maybe that would make it more clear.

[00:22:58] Speaker 00:
The specification defines a local interconnect as conductors that connect features within a circuit.

[00:23:08] Speaker 00:
So that doesn't mean that it's necessarily a channel that is connecting components, connecting a figure of laterally.

[00:23:18] Speaker 01:
In figure three, does the conductor between these bit line conductors, do they lie entirely in the layer?

[00:23:28] Speaker 00:
So they do.

[00:23:30] Speaker 00:
The local interconnect itself is in that local interconnect layer.

[00:23:37] Speaker 00:
But it can connect signals vertically through the layer.

[00:23:41] Speaker 00:
So the lower level connector can connect up through the layer, through that local interconnect, in the local interconnect layer, up to signals up above.

[00:23:52] Speaker 00:
The signals route vertically.

[00:23:54] Speaker 00:
But the local interconnect layer can also route the signals laterally.

[00:23:58] Speaker 00:
The figure three allows that to occur laterally, but the claim also allows local interconnects that can connect vertically.

[00:24:09] Speaker 01:
Now you just switched from the figure to the claim.

[00:24:13] Speaker 01:
And what at least I've been trying to understand is precisely what figure three shows.

[00:24:19] Speaker 01:
And I don't understand how, I guess I keep hearing you say two diametrically opposite things.

[00:24:24] Speaker 00:
Figure three is open to interpretation.

[00:24:27] Speaker 00:
And that's also what Monterey admitted below.

[00:24:30] Speaker 00:
That you can, that it could be connecting signals vertically.

[00:24:34] Speaker 00:
But it could also be connecting signals laterally.

[00:24:37] Speaker 00:
You just can't tell from the figure because there's only one contact.

[00:24:42] Speaker 00:
There's not a second contact.

[00:24:43] Speaker 00:
If there was another contact shown, and that's that dotted line contact on the interconnect square.

[00:24:50] Speaker 01:
If there was another contact... So like the little 16... 16C dotted line.

[00:24:56] Speaker 00:
That's right.

[00:24:56] Speaker 01:
And what is that supposed to connect to?

[00:24:58] Speaker 00:
So that's a contact below.

[00:25:00] Speaker 00:
So the patent says that that connects to the polysilicon structures in the active regions on a layer below.

[00:25:08] Speaker 00:
What you need is a second contact to understand whether it's connecting vertically.

[00:25:14] Speaker 00:
So the second contact could be stacked right on top, and then it would be connecting vertically.

[00:25:19] Speaker 00:
But if it is instead, if there's another contact that was on the other end on the right side of the local interconnect, then it would be routing laterally.

[00:25:29] Speaker 00:
But we just don't know, because the figure doesn't show it.

[00:25:32] Speaker 00:
And so there's no requirement in this figure that it would be routing laterally, because there's no second contact that shows lateral routing.

[00:25:41] Speaker 04:
OK, but let's be clear about what the two different plane constructions are.

[00:25:49] Speaker 04:
understand the board's construction.

[00:25:52] Speaker 04:
They're saying you could have local interconnects at another layer, but all that's required is that the single layer be exclusively concerned with interconnects and not do anything else.

[00:26:06] Speaker 04:
Whereas in the patentee's construction, they're saying all the local interconnects have to be at one layer.

[00:26:13] Speaker 04:
They can't be in part on the top layer.

[00:26:18] Speaker 04:
And I understand

[00:26:20] Speaker 04:
Do you agree that my description of the two different plane constructions is correct?

[00:26:27] Speaker 00:
No, Your Honor, I would disagree with that because the board's construction does allow for a single, like one conductive layer is what the board says, but Monterey's construction specifically says

[00:26:39] Speaker 00:
routing the bit line signals and the word line signal along that layer.

[00:26:44] Speaker 00:
That's the distinction that they're trying to make, which isn't accepted.

[00:26:47] Speaker 02:
Can I try to see if I can understand this?

[00:26:51] Speaker 02:
Figure 3 is a top-down view of the interconnect layer, right?

[00:26:55] Speaker 01:
That's right.

[00:26:55] Speaker 02:
And underneath that is a polysilicon layer, and underneath that is the silicon substrate where the active regions are, right?

[00:27:02] Speaker 02:
And then above this layer, we can't see it in this top-down view, but above that,

[00:27:06] Speaker 02:
will be metal layers, one for the bitlines and one for the word model.

[00:27:12] Speaker 02:
And so we have these dotted boxes and rectangles showing the contact region for all these different interconnects to layers below.

[00:27:22] Speaker 02:
So for the bitline interconnect 38, we see a dotted line 16C showing the contact region for things below, like the polysilicon layer and the substrate.

[00:27:34] Speaker 02:
What we don't know is

[00:27:36] Speaker 02:
Where would the contact region be for the bit line layer itself that's above this figure three?

[00:27:45] Speaker 02:
If there was another dotted box from the bit line layer that covered the 16C dotted box, then there wouldn't be any lateral displacement.

[00:27:59] Speaker 02:
Then there wouldn't be any signal running along the length or width of this

[00:28:05] Speaker 02:
bit line interconnect 38, right?

[00:28:08] Speaker 00:
Yes, that's right.

[00:28:10] Speaker 02:
But on the other hand, if the dotted box that would correspond to the contact region for the bit line layer was offset from 16C and was, say, on the other end of bit line interconnect 38, then what you would have would be a signal traveling along the length of bit line interconnect 38.

[00:28:35] Speaker 02:
so that it could connect up with the bit line layer above, right?

[00:28:41] Speaker 00:
Yes, that's exactly correct.

[00:28:42] Speaker 02:
But from figure three and from the patent itself, we don't know which way, where that contact region for the bit line layer would actually be located above bit line interconnect 38.

[00:29:00] Speaker 02:
It could be right over 16C or it could be offset.

[00:29:04] Speaker 02:
And so figure three by itself doesn't tell us one way or another whether it is a requirement for the interconnection to be laterally displaced.

[00:29:19] Speaker 00:
Yes, that's right.

[00:29:20] Speaker 00:
So even if the patentee had limited his invention to figure three, which I don't think is reflected in the prosecution history, but even if that were so, figure three doesn't limit the claim to lateral routing.

[00:29:37] Speaker 04:
OK, so does that mean that the board's description of figure three on page 87 is incorrect?

[00:29:45] Speaker 04:
Where they say, oh, well, they say the embodiment on figure three

[00:29:50] Speaker 04:
illustrates routing the lines and the line signals along a single interconnect line.

[00:29:58] Speaker 00:
I think it is incorrect, Your Honor, and the board was a little bit inconsistent in its descriptions here, because it did also explain that Figure 3 doesn't disclose those locations, and thus doesn't necessarily disclose lateral routing.

[00:30:13] Speaker 02:
So when it said what it said at the bottom of A65, wouldn't that be a more accurate description by the board of what's going on in Figure 3?

[00:30:23] Speaker 02:
When it said, although Figure 3 shows bit line signals can be routed horizontally,

[00:30:28] Speaker 02:
and a global wordline signal can be routed vertically.

[00:30:31] Speaker 02:
Neither the specification nor claims require such routing.

[00:30:35] Speaker 02:
So in that way, the claims perhaps encompass both lateral displacement situations and no lateral displacement situations.

[00:30:45] Speaker 00:
Yes, that is correct.

[00:30:51] Speaker 00:
I wanted to briefly address Monterey's assertion that it's actually the word local in the word local interconnect that creates this lateral displacement requirement.

[00:31:01] Speaker 00:
This is a new argument that wasn't raised in the opening brief.

[00:31:05] Speaker 00:
They never raised the construction of local interconnect.

[00:31:09] Speaker 00:
They only emphasized the patent owner's amendment to add the word single and the claims

[00:31:14] Speaker 00:
requirement that the interconnect layer has to include both word lines.

[00:31:19] Speaker 04:
Let's look at 1262, the statement we were focusing on earlier.

[00:31:25] Speaker 04:
It's happening to observe that all of the runs for the bit lines and the word lines are provided in a single layer of Figure 3.

[00:31:34] Speaker 04:
If they had left out the reference to Figure 3 there, that would

[00:31:41] Speaker 04:
be a statement of the patentee's construction, correct?

[00:31:50] Speaker 00:
Yes, as to the single-layer aspect.

[00:31:53] Speaker 00:
Yes, Your Honor.

[00:31:55] Speaker 04:
So the reason that you say that this doesn't help them is because of the reference to Figure 3?

[00:32:02] Speaker 00:
No, because the

[00:32:07] Speaker 00:
The reference here in the prosecution history is just to the single layer aspect.

[00:32:12] Speaker 00:
And the patent owner may have attempted to distinguish OSADA, but not on the basis of whether or not there was lateral routing.

[00:32:20] Speaker 00:
They're talking about the single layer.

[00:32:22] Speaker 00:
And that single layer is actually in the claim language already.

[00:32:26] Speaker 00:
It calls for a single local interconnect layer.

[00:32:29] Speaker 00:
So there's no question about whether or not there should just be a single layer of local interconnects, including both the bid line and the word line interconnect.

[00:32:38] Speaker 00:
The distinction is based on this new lateral routing requirement that Monterey is attempting to import into the claims.

[00:32:47] Speaker 02:
There was some kind of disclaimer, but it was a very limited type of disclaimer that happened in the prosecution history that has nothing to do with a single interconnect layer having laterally displaced connections where signals, bit line signals are being routed horizontally across the interconnect layer.

[00:33:05] Speaker 02:
None of that is in the prosecution history, right?

[00:33:09] Speaker 00:
Yes, that's right.

[00:33:11] Speaker 02:
And as you've stated before, the- And that's what they've come here to ask for us to read into the claim based on that kind of an interpretation of what happened in the prosecution history.

[00:33:23] Speaker 00:
Yes, that's right.

[00:33:25] Speaker 00:
And that's the problem.

[00:33:26] Speaker 01:
You just agree that there was some kind of disclaimer.

[00:33:29] Speaker 01:
What do you think the scope of that disclaimer was?

[00:33:33] Speaker 00:
It's limited to this idea of there being a single layer.

[00:33:38] Speaker 00:
That's the amendment that the... Single layer of what?

[00:33:41] Speaker 00:
Of interconnects.

[00:33:43] Speaker 00:
Of interconnects.

[00:33:44] Speaker 00:
So there is just one conductive layer of local interconnects rather than multiple layers.

[00:33:51] Speaker 02:
The bit-line layer interconnects and the word-line layer interconnects have to be in this one layer.

[00:33:56] Speaker 00:
Yes, that's right.

[00:33:58] Speaker 02:
And that layer is exclusively dedicated to interconnects.

[00:34:01] Speaker 00:
Yes, that's right.

[00:34:02] Speaker 02:
That's the disclaimer.

[00:34:04] Speaker 00:
That is.

[00:34:05] Speaker 00:
That is.

[00:34:06] Speaker 00:
That's the distinction that was made.

[00:34:08] Speaker 04:
No, so there can be interconnects formed in other layers, but this is... How is that consistent with what they said?

[00:34:21] Speaker 00:
Because the patentee said that there has to be one layer exclusively dedicated to local interconnect.

[00:34:28] Speaker 04:
That's not what this says.

[00:34:30] Speaker 00:
Not what the patentee said in the prosecution history.

[00:34:33] Speaker 04:
No, but we'll focus on what they said in the prosecution history.

[00:34:36] Speaker 04:
They're saying that all the runs to the bit lines and word lines are provided in a single layer.

[00:34:42] Speaker 04:
So that means all the local interconnects are provided in a single layer, correct?

[00:34:47] Speaker 00:
That is correct, but the patent also defines a local interconnect layer as... No, no, no, no.

[00:34:54] Speaker 04:
Stick with the prosecution history, okay?

[00:34:57] Speaker 04:
Because the prosecution, the theory is that the prosecution history limited the patent to a subset of what was originally claimed.

[00:35:08] Speaker 04:
And so they're saying all the local interconnects are provided in a single layer.

[00:35:13] Speaker 04:
If you leave out figure three,

[00:35:15] Speaker 04:
That would seem to be fully consistent with the patentee's construction and inconsistent with the board's construction.

[00:35:26] Speaker 04:
Don't.

[00:35:27] Speaker 00:
Well, it's not inconsistent with the board's construction.

[00:35:31] Speaker 00:
The board's construction says one conductive layer containing the non-global interconnects, including interconnects for both bit lines and the word line.

[00:35:39] Speaker 04:
Another board's construction can be local interconnects at another layer, because the board's construction only requires that the single layer itself be exclusively concerned with interconnects.

[00:35:51] Speaker 00:
I don't think that that is what the patent owner was disclaiming here, that there could not be interconnects in other layers.

[00:36:00] Speaker 04:
I don't understand.

[00:36:01] Speaker 04:
I mean, the language leaving out the reference to figure three seems to be pretty clear on its face, saying all the interconnects happen in one layer.

[00:36:10] Speaker 00:
I think there is ambiguity there that there could be that one layer could contain all of these types of interconnects and that some of the other layers may include those types of interconnects too, but there must be a single layer that has all of these interconnects.

[00:36:26] Speaker 02:
Has the patent owner in this appeal ever argued that under their understanding of the claim, there can be no interconnects in any other layer than the single interconnect layer?

[00:36:37] Speaker 00:
No, that's not an argument that the patent owner has made.

[00:36:42] Speaker 02:
Their understanding of the prosecution history disclaimer is more devoted to this idea of having laterally displaced interconnections along the single interconnect layer.

[00:36:54] Speaker 00:
Yes, that is what the dispute here is about.

[00:36:57] Speaker 00:
And that's what Monterey's construction is about.

[00:37:00] Speaker 00:
That's what they've been focusing on in their briefing.

[00:37:06] Speaker 01:
Was there agreement in this case about what this word runs means as a noun?

[00:37:14] Speaker 00:
No, Your Honor.

[00:37:15] Speaker 00:
And that's something that the patent owner said in the prosecution history.

[00:37:20] Speaker 00:
It's not clear what was meant there.

[00:37:23] Speaker 00:
That's also an ambiguous use of the term.

[00:37:26] Speaker 00:
And there's no agreement from either side about or the board on what that meant.

[00:37:32] Speaker 00:
But runs aren't necessarily lateral routing either.

[00:37:36] Speaker 00:
They run a connection between features in the circuit, which is what a local interconnect is defined to have.

[00:37:44] Speaker 00:
It connects features within a circuit, and runs can connect vertically.

[00:37:48] Speaker 00:
They don't necessarily have to connect laterally.

[00:37:52] Speaker 04:
OK.

[00:37:52] Speaker 04:
I understand that.

[00:37:53] Speaker 04:
But runs means local interconnects, right?

[00:37:56] Speaker 00:
It does.

[00:37:58] Speaker 00:
Well, I don't know what it means exactly here, Your Honor.

[00:38:02] Speaker 04:
But it's referring to local interconnects.

[00:38:05] Speaker 00:
What else could it mean besides local interconnects?

[00:38:09] Speaker 00:
The way the signal runs.

[00:38:12] Speaker 00:
But I think they are referring to local interconnects in this particular sentence on page 1262.

[00:38:25] Speaker 04:
Anything else?

[00:38:36] Speaker 03:
To your honors, I'd like to clarify a few points of confusion or ambiguity that I think are really critical to resolving the issues.

[00:38:45] Speaker 03:
First of all, my friend on the other side moved back and forth between the term interconnects and local interconnects.

[00:38:51] Speaker 03:
And there is a very important distinction between them.

[00:38:54] Speaker 02:
Could you just help us and give us your articulation of what single interconnect layer means, or single local interconnect layer means in this claim?

[00:39:04] Speaker 03:
Yes, your honor.

[00:39:04] Speaker 02:
In one sentence, what is it?

[00:39:06] Speaker 03:
It is a single layer in which the local interconnects for the bit lines and the word line are on that same layer and they laterally displace the connections.

[00:39:22] Speaker 03:
so that they can make lateral connections to the next layers.

[00:39:25] Speaker 03:
And that's shown by the combination.

[00:39:27] Speaker 02:
And so if we were to conclude, after looking at the prosecution history, that there isn't any requirement of lateral displacement for that connection, then is that the end of the case?

[00:39:42] Speaker 02:
At least on this issue, I understand there's that substantially oblong piece.

[00:39:46] Speaker 03:
So the horizontal requirement or lateral displacement requirement is critical to the dispute.

[00:39:55] Speaker 03:
And that is evidence, though.

[00:39:57] Speaker 03:
That requirement is evidence.

[00:39:59] Speaker 03:
For example, at appendix 1812 to 1813, and this is a place where the prosecution history ties figure three once again directly to the amended claim language.

[00:40:10] Speaker 03:
It's also, the questions you asked, Judge Chen, I understand about the fact of the contacts and showing them in other dimensions.

[00:40:23] Speaker 03:
That is explained, for example, in Column 13 in connection with the description of Figure 3.

[00:40:29] Speaker 03:
It shows or it tells us that those local interconnects in Figure 3 connect to components that are in Figure 2.

[00:40:39] Speaker 03:
In our opening brief at page 45 We provided a sort of an overlay of figures two and three where we show the lateral displacement happening with respect to the upper contacts Contact points that are depicted in figure two

[00:40:55] Speaker 03:
And I would say at the end of the day, it's important not to lose sight of the forest for the trees here.

[00:41:03] Speaker 03:
AMD recognized in its petition what this prosecution history language means.

[00:41:09] Speaker 03:
And the drawing at appendix 183 from AMD itself with respect to OSADA tells us how it is that the patentee distinguished OSADA.

[00:41:18] Speaker 03:
The construction that the board gave and that my friend on the other side seeks would have the result at the end of the day of encompassing

[00:41:25] Speaker 03:
Osada's design.

[00:41:26] Speaker 02:
Neither figures two nor three show us the bit line layer or word line layer overlapping the interconnect layer, right?

[00:41:38] Speaker 03:
I believe they do, Your Honor.

[00:41:41] Speaker 03:
I think it's in the description of the patent in terms of those components.

[00:41:45] Speaker 02:
I could see some kind of overlap in figures two or three of the bit line layer.

[00:41:53] Speaker 02:
Where would that be?

[00:41:56] Speaker 02:
Your Honor, I see your active regions.

[00:41:59] Speaker 02:
I see your interconnects.

[00:42:02] Speaker 02:
Sure.

[00:42:03] Speaker 03:
So I think it's important to pay attention here to the design

[00:42:11] Speaker 03:
of the local interconnects and the fact that they are substantially oblong.

[00:42:16] Speaker 03:
That is the whole purpose.

[00:42:17] Speaker 03:
Designers don't waste real estate in these very precious semiconductor devices for no reason.

[00:42:24] Speaker 03:
If they wanted to route it only vertically, they would create square

[00:42:27] Speaker 03:
interconnects that would not be local interconnects.

[00:42:30] Speaker 03:
And that's what OSADA does.

[00:42:32] Speaker 03:
But in figure three, we have the substantially oblong interconnects.

[00:42:36] Speaker 02:
And the entire purpose of using that real estate to go in a... Can you say substantially oblong, you mean these rectangular interconnects?

[00:42:44] Speaker 03:
I mean based on the description that's in the in the patents written description.

[00:42:48] Speaker 02:
Right.

[00:42:50] Speaker 02:
Okay.

[00:42:51] Speaker 03:
And the purpose of that is the ladder of displacement.

[00:42:54] Speaker 03:
Otherwise, they wouldn't waste that real estate.

[00:42:55] Speaker 03:
They would just create a square, as Osada did or O did, so they could have a vertical routing.

[00:43:00] Speaker 02:
Has it ever been your understanding of single interconnect layer that every single interconnect in a memory cell has to be on the single interconnect layer, or there can still be interconnects on other layers?

[00:43:12] Speaker 03:
No, Your Honor, the distinction is between local interconnects and just interconnects that are not local.

[00:43:18] Speaker 03:
So the local interconnects happen anyway.

[00:43:21] Speaker 02:
Wait, wait, wait.

[00:43:23] Speaker 02:
You said no to my question as to whether it's your interpretation that all interconnects have to be on the single interconnect layer, right?

[00:43:33] Speaker 02:
In other words, your claim interpretation is open to have an interconnect on other layers other than the single interconnect layer.

[00:43:41] Speaker 03:
And the word local.

[00:43:43] Speaker 03:
Correct.

[00:43:43] Speaker 03:
It is not open to having local interconnects in other layers with respect to the bit lines and the word line.

[00:43:50] Speaker 03:
Now, there are other dependent claims that further restrict

[00:43:53] Speaker 03:
Claim a with respect to the nature of the local interconnects and what has to be in that single layer But with respect but claim aid itself is directed to the bit lines and the word line and with respect to those all of the local interconnects for those Which are the structures that laterally displays have to be in that one single layer?