[00:00:08] Speaker 05: Thank you. [00:00:11] Speaker 02: Thank you, Your Honor. [00:00:12] Speaker 02: May it please the Court. [00:00:14] Speaker 02: So this appeal involves two separate IPRs, and I'm going to start sequentially with the 989 IPR. [00:00:22] Speaker 02: This IPR relates to the reference, the Vorbach reference. [00:00:27] Speaker 03: And I think that... If we affirm on Vorbach, then we don't get to Pick 16, right? [00:00:33] Speaker 03: Or don't need to reach the Pick 16 question? [00:00:35] Speaker 02: That's correct. [00:00:37] Speaker 05: but it's not true vice versa, right? [00:00:43] Speaker 02: That is correct because of the application note that was used for certain claims in the PIC 16 IPR. [00:00:54] Speaker 02: So with respect to the single register write operation, so I think when you need to start with the specification of the 407 patent to understand [00:01:06] Speaker 02: what it means to configure the, in the patent, the programmable digital circuit block, the PDCB, for performing the digital functions. [00:01:16] Speaker 05: It turns on whether the reuse is substantial enough, right? [00:01:20] Speaker 02: This turns on, that's the second issue, Your Honor, which I flipped them for oral argument. [00:01:26] Speaker 02: The first issue in the briefing is the substantial reuse [00:01:30] Speaker 02: and whether that constitutes a programmable digital circuit block. [00:01:35] Speaker 05: Yeah, that was my question. [00:01:38] Speaker 05: It all depends on whether Vorbach shoves substantial re-use, right? [00:01:46] Speaker 02: I think, in my mind, they are separate issues, either of which could be dispositive one way or the other. [00:01:54] Speaker 02: I think that you have to have, in this IPR, you have to have both a programmable digital circuit block, which invokes whether there's substantial reuse of circuit elements, and you also have to satisfy the single register write operation. [00:02:09] Speaker 02: I'm talking about the single register write operation, if I could. [00:02:13] Speaker 02: I'm sorry to confuse you, your honor. [00:02:19] Speaker 04: Single register write operation. [00:02:21] Speaker 02: Single register write operation. [00:02:22] Speaker 02: So, and this invokes the requirement that the block be configured to perform digital functions. [00:02:30] Speaker 02: And so the question is, what does the 407 patent say about the configuration of the programmable digital circuit block? [00:02:38] Speaker 05: But on that one, the F for it performs all the functions. [00:02:42] Speaker 05: Right? [00:02:44] Speaker 05: And that the only use of the M-Berry, which is also necessary, is to connect to the outs from the chip to the outside. [00:02:52] Speaker 02: Right? [00:02:53] Speaker 02: The FPLU register is described as configuring the functions of the block. [00:03:01] Speaker 05: And the M-Berry performs the function of the interconnections. [00:03:05] Speaker 02: To the outside. [00:03:06] Speaker 02: To the outside world. [00:03:07] Speaker 02: But that's essential to performing the functions, Your Honor. [00:03:09] Speaker 02: Because in the specification, it talks about how the programmable digital circuit blocks are 8-bit circuit modules that can be programmed to perform a variety of digital functions. [00:03:20] Speaker 02: It goes on, and this is in column 2, it goes on in column 2 to explain that programmable digital circuit blocks can be figured as these various functions that are listed there, each of which, by the way, requires an input and an output. [00:03:33] Speaker 02: And then the specification later in column 2 in line 21 says the programmable digital circuit blocks can be configured [00:03:40] Speaker 02: to be coupled in series or in parallel to handle more complex functions. [00:03:43] Speaker 02: So their outputs are then, if it's in serial, they're routed downstream to the next block, which performs some additional processing on the data. [00:03:51] Speaker 02: And there's a third option. [00:03:53] Speaker 02: There's serial parallel, and then there's the situation where the block is configured by itself to perform the function. [00:04:00] Speaker 02: And so you have to be able to configure that MPLU register [00:04:05] Speaker 02: to know whether the outputs are going to be sent to another programmable digital circuit block or not, or whether they're being used in parallel to perform parallel processing of the data. [00:04:19] Speaker 02: And without that, you're not configuring the PDCB to perform the function, because you're not going to just, a designer is not going to leave it unknown as to how the external configuration of that block is. [00:04:34] Speaker 02: because the data. [00:04:35] Speaker 05: So the question is whether when the claim says pre-determined digital functions, whether that includes connecting the chip to the outside. [00:04:42] Speaker 02: That's correct, Your Honor. [00:04:44] Speaker 02: And I think based on especially column two lines, roughly lines three down to 23, it's clear that when it talks about configuring in the 407 patent, it is including that interconnection to the other elements in the larger array. [00:05:00] Speaker 02: And that's also consistent in [00:05:02] Speaker 02: the Vorbach reference itself. [00:05:13] Speaker 02: There's a definition section, I believe it is. [00:05:23] Speaker 02: in the four boxes in column 17. [00:05:26] Speaker 01: Can you just go back for a second to column two of the 407? [00:05:35] Speaker 01: What language in there supports the idea, which I think I heard you articulate, that for any digital function, connection to the outside world is part of configuring, as opposed to [00:05:53] Speaker 01: a digital function of communicating through a serial port would be one example, but others might not. [00:06:02] Speaker 02: I understand, Your Honor. [00:06:03] Speaker 02: I think it's in the larger context of [00:06:05] Speaker 02: explaining in particular that this is a column two line, I think it's 21 to 23, that the programmable digital circuit block can be configured to be coupled in serial or parallel to handle more complex operations. [00:06:18] Speaker 02: Implied in that is that it wouldn't be configured in serial or parallel to perform these more simple operations, but it still would need to be set accordingly so that the array [00:06:30] Speaker 02: routes the data appropriately within the array. [00:06:33] Speaker 02: So it doesn't route it to another programmable digital circuit block that isn't expecting that data and that performs some other operation on the data when it shouldn't be. [00:06:42] Speaker 02: This is how the overall array shown in Figure 1 is configured. [00:06:54] Speaker 02: So it depends on [00:07:00] Speaker 02: what is necessary to perform the digital function. [00:07:04] Speaker 05: I'm sorry, I didn't hear the first part. [00:07:10] Speaker 05: I thought you said that the Enchloric is not necessary to perform the functions within the chip. [00:07:20] Speaker 02: I think that the interconnections are essential to determining the proper operation of that programmable digital circuit block and how [00:07:30] Speaker 02: what data it uses. [00:07:31] Speaker 05: But you said that the inquiry doesn't help perform functions within the chip. [00:07:37] Speaker 05: It connects to the outside. [00:07:39] Speaker 05: And I'm not understanding from that view of it what this language has to do with whether connecting to the outside is a function within the meaning of the point. [00:07:52] Speaker 02: Well, Your Honor, I think it's the reading of the [00:07:59] Speaker 02: I focused on column two and how it talks about configuring this data, this block rather, serial parallel or. [00:08:14] Speaker 02: Well, that's implicitly the construction the board adopted. [00:08:18] Speaker 02: We're talking about just configuration on certain logic elements within the programmable digital circuit block. [00:08:26] Speaker 02: But in figure one, it clearly shows that the inputs and outputs are also part of the programmable digital circuit block, along with the data registers and configuration registers. [00:08:40] Speaker 02: limited to the selectable logic circuits that are shown in Figure 1. [00:08:46] Speaker 02: But in the prior art, in Vorbach, that's essentially what the board did. [00:08:50] Speaker 02: They took this Figure 1 and narrowed it down to just the selectable logic circuits 30 and said you only have to configure those. [00:08:58] Speaker 02: That's all that's required in this claim. [00:09:01] Speaker 02: But that's not really consistent with [00:09:03] Speaker 02: the broader teachings of the patent, as I say, in particular it. [00:09:08] Speaker 04: What about the lower one third of column five of the 407 patent, which appears to be making a distinction between configuring something and then interfacing that same thing? [00:09:25] Speaker 04: Are you referring to the first sentence [00:09:28] Speaker 04: starting at line 43 maybe. [00:09:32] Speaker 04: In general, the number of bits in the configuration data is sufficiently small to enable the configuration registers to be programmed on the fly so that the programmable digital circuit block 100 can be dynamically configured and interfaced. [00:09:46] Speaker 04: And then further down in the new paragraph [00:09:50] Speaker 04: The connections 50A to 50E between the configuration registers 50 enable the configuration registers to properly configure the programmable digital circuit block 100 to any one of the predetermined digital functions and to properly interface the programmable digital circuit block 100 with other programmable digital circuit blocks in series or in parallel. [00:10:18] Speaker 04: Configure here seems to exclude interfacing, whatever interfacing means, and perhaps interfacing is talking about these kinds of interconnections, which is what the mClurig is about in Vorbach. [00:10:34] Speaker 02: I think that setting the interconnection is part of the configuration. [00:10:42] Speaker 02: And I understand that when it wants to be more specific about, it's talking about the relationship of one block to another block. [00:10:49] Speaker 02: It does use this term interface. [00:10:51] Speaker 02: I'm sorry, interconnection. [00:10:53] Speaker 04: So doesn't it seem like this passage that we just wrote together makes configuring and interfacing two different things? [00:11:03] Speaker 02: Well, I disagree, Your Honor. [00:11:05] Speaker 02: Based on the totality of the patent, [00:11:08] Speaker 02: but also if you look up above in the same column, column five, line looks like 28 down to the end of that paragraph at line roughly 42, it talks about the configuration data includes, and then it lists a series of different types of configuration data, and number five, [00:11:26] Speaker 02: is bits for indicating and configuring the interface. [00:11:29] Speaker 02: So there it's talking about configuring the interface, so it's using those two terms side by side. [00:11:34] Speaker 02: The interface between adjacent PDCBs that are coupled together, and then in parentheses it talks about whether it be in serial, cascading them for serial or for parallel interfacing. [00:11:48] Speaker 02: And Forbach also has a messy patent. [00:11:50] Speaker 02: I'm sorry? [00:11:51] Speaker 04: Nothing, keep going. [00:11:53] Speaker 02: In Vorbach, it has in column 17 a definition of configuring that includes determining the function and interconnection of a logic unit, a FPGA cell or PAE. [00:12:05] Speaker 02: So within the context of configuring, even in the prior art reference, it's including the two subcategories of... That's extrinsic evidence. [00:12:14] Speaker 02: That's true, you're on. [00:12:15] Speaker 02: That's true. [00:12:17] Speaker 02: But within the 407 patent, I think that [00:12:19] Speaker 02: plenty of references and we've just touched on a couple here, probably the more significant ones, that explain that the configuration of the block to perform its function, that's what it does, but it includes this idea of the interconnection. [00:12:34] Speaker 01: In Vorbach, which I know you were trying to talk about a little bit earlier, is there any digital function that can be performed without an interconnection? [00:12:48] Speaker 02: No, because all of the, based on my recollection of the records, I'm not aware of any, because all of these different functions are going to require an input and an output at least. [00:13:03] Speaker 02: And so it has to know where the data is going to be routed within the larger array for the overall operation of the [00:13:11] Speaker 02: device to work properly. [00:13:13] Speaker 02: It can't be sending data to a different PAE than PAE. [00:13:19] Speaker 02: PAE? [00:13:19] Speaker 02: PAE, yes. [00:13:21] Speaker 02: What does that stand for? [00:13:24] Speaker 02: Processing Array Elements, I think it is. [00:13:29] Speaker 02: That's shown in Figure 1, for example, of VORPA. [00:13:33] Speaker 01: And it's your position that the M flu reg is required for that, and therefore is required for any digital function of the block. [00:13:48] Speaker 02: That is our position, Your Honor. [00:13:52] Speaker 02: I've exceeded my time and have barely touched on the issues. [00:13:54] Speaker 05: We'll give you two minutes, Your Honor. [00:13:56] Speaker 02: I'm sorry, Your Honor. [00:13:56] Speaker 05: We'll give you two minutes, Your Honor. [00:13:58] Speaker 02: Thank you, Your Honor. [00:14:09] Speaker 00: Good morning, Your Honors. [00:14:10] Speaker 00: May it please the Court? [00:14:14] Speaker 00: With respect to the single-register right limitation and Borbach's application to that limitation, as we expressed in our briefing, we believe that the correct way to look at this situation is that the [00:14:31] Speaker 00: functions are internally facing within a PAE and interconnections are outwardly facing between one PAE and a cascade of other PAEs in an array. [00:14:43] Speaker 00: We can see this in the figure. [00:14:46] Speaker 05: When the PAEs are all in the same chip or outside the chip? [00:14:53] Speaker 00: PAEs, the way I would think about it are. [00:14:56] Speaker 05: Interconnecting to other PAEs is within the same chip [00:15:00] Speaker 00: I believe the PAEs are their own individual chips, and they're connecting with other chips. [00:15:08] Speaker 05: And so you can have an array of chips, but each... So in your view, interconnection is limited to connecting the chip to the app side? [00:15:17] Speaker 00: Correct. [00:15:19] Speaker 00: And as we can see, for instance, in Borbach, Figure 2, page 1131 of the appendix, [00:15:31] Speaker 00: which shows a single PAE. [00:15:39] Speaker 00: And within the single PAE, this is where the functions in question are happening. [00:15:45] Speaker 00: The EALU component 208 is the component that performs the functions of arithmetic, logic, and other special functions such as trigonometry and counting. [00:15:59] Speaker 00: the EALU relies on other registers including 204 and 205 and the multiplexer 206 to be able to complete those functions. [00:16:11] Speaker 00: But with claim one of this [00:16:14] Speaker 00: of the patent in question is reciting is the ability to perform a plurality of digital functions and that is what is happening within the four corners of this PAE. [00:16:29] Speaker 00: The multiple digital functions being arithmetic, logic, and other special functions such as trigonometry and counting. [00:16:38] Speaker 00: This way of viewing the prior art and the patent in question is how the parties litigated this case before the board. [00:16:51] Speaker 00: And we can go back through the record and readily see that. [00:16:56] Speaker 00: For instance, in the board's decision instituting review, pages 293 to 294 of the appendix. [00:17:09] Speaker 00: At the bottom of page 293, the board notes that Pat Noner Monterey argues that four box M blue reg means that even with a single F blue reg, four box PAE is not configured with a single register write operation. [00:17:26] Speaker 00: The board goes on to say, while the MPUREG controls a PAE's interconnection information, it does not control the function of the PAE itself, only how the PAE may interact with other such elements. [00:17:41] Speaker 00: After institution, this way of looking at the technology continued. [00:17:48] Speaker 00: Monterey and its own patent owner's response, page 406 of the appendix. [00:17:55] Speaker 00: argued that M. plurag is required, since this is the last sentence on page 406 of the appendix, a right of M. plurag is required since it configures the connections of the EALU and accordingly the internal connections being bolded and italicized of the PAE are required. [00:18:22] Speaker 00: AMD sought to pin down this point in its reply brief, page 437 of the appendix, where AMD argued that Monterey still has not advanced a construction, essentially that would require [00:18:49] Speaker 00: interconnections to be an essential part of the writing to a register to do interconnections is not necessary to proclaim one to read on the prior art. [00:19:12] Speaker 00: So we believe the record is clear that this is how the parties viewed it before the board. [00:19:18] Speaker 00: I think the arguments in the briefing before this court that now that M. Plurag is necessary to configure interconnections and that interconnections matter within the claim language is incorrect. [00:19:38] Speaker 00: And again, representative claim, claim one. [00:19:40] Speaker 00: only requires a programmable digital circuit block that is configurable to perform any one of the plurality of predetermined digital functions. [00:19:51] Speaker 00: Interconnections is a term of art in this field, and it's not used in claim one, only functions are. [00:20:04] Speaker 00: Unless the court has any further questions, I will return my time to the court. [00:20:34] Speaker 02: Thank you, Your Honor. [00:20:35] Speaker 02: Just to pick up on this point of the interconnections, I think that if you look at not only the portions of column two that we talked about earlier, and there are other portions, in particular in column five that we also talked about, column five, lines 28 to 43, it looks like, it's clear that configuration in this patent, it does include the interrelationship between one block and another block. [00:21:01] Speaker 02: It's not just insert. [00:21:03] Speaker 05: How do you make out of the language of the claim that says to perform any one of the corrales if we determine each of the functions? [00:21:10] Speaker 05: So even if interconnections were one of those functions, you don't need the M for it to perform every function. [00:21:20] Speaker 02: Yes, Your Honor. [00:21:21] Speaker 02: And I'm not arguing that all functions have to be performed. [00:21:25] Speaker 02: My argument is not based on that. [00:21:27] Speaker 02: I'm simply saying that for any of these individual functions, [00:21:32] Speaker 02: The interrelationship between that block and another block has to be defined in the MPLU register for the overall array of blocks to function properly. [00:21:46] Speaker 02: One has to know who is communicating with and where that data is going and so that the receiving block gets the right information and often some [00:21:58] Speaker 02: erroneous information. [00:21:59] Speaker 02: So that register has to be written to, to configure that relationship before it performs the function. [00:22:06] Speaker 02: It can't perform the function until that register is configured. [00:22:10] Speaker 02: Also in claim to, dependent claim to, it talks about how the block is configured into a serial arrangement. [00:22:19] Speaker 02: So that's, again, that's an external relationship. [00:22:22] Speaker 02: I think it's also [00:22:23] Speaker 02: other dependent claims, but claim 16, which depends from claim 15, 15 is a method of configuring a programmable digital circuit block. [00:22:33] Speaker 02: Claim 16 says wherein said configuring, said configuring includes configuring the programmable digital circuit block into a serial arrangement. [00:22:41] Speaker 02: Claim 17 presides a parallel arrangement. [00:22:46] Speaker 02: So it's not just, whether, it's not just the [00:22:54] Speaker 02: FPLU register that has to be set, the MPLU register also has to be set before that block performs its logic function.