[00:00:00] Speaker 04:
Number 221577, Monterey Research Against Vidal.

[00:00:06] Speaker 02:
Mr. Jackson, whenever you're ready.

[00:00:08] Speaker 02:
Thank you, Your Honor.

[00:00:12] Speaker 02:
So the board's construction of multi-queue storage device recognized that it's a storage device that has data organized into multiple queues, and it's explained that that construction was out without regard to whether the logic or component that organizes or manages the queues

[00:00:34] Speaker 02:
are internal or external to the storage device.

[00:00:36] Speaker 02:
So the board recognized there could be an internal control, what I'll call control logic, or it could be external, that is outside of the storage device.

[00:00:46] Speaker 00:
And that's not, that claim construction is not challenged on appeal, correct?

[00:00:50] Speaker 00:
That's correct.

[00:00:51] Speaker 00:
Okay.

[00:00:51] Speaker 02:
That's correct.

[00:00:52] Speaker 02:
And so, but I think the distinction there and the recognition by the board about internal versus external is important because the only device in the Joshi reference that has those multiple cues is arguably the buffer memory 38.

[00:01:09] Speaker 02:
And as you can see in figure one of Joshi, the datapath controller 43 in particular is outside.

[00:01:16] Speaker 02:
It's external to that storage, that buffer memory 38, the storage device.

[00:01:23] Speaker 02:
And all of the board's conclusions are premised on the conclusion that it's the datapath controller 43 plus the buffer memory 38 that make up the claimed storage device.

[00:01:35] Speaker 00:
Do you contend that the datapath controller 43 doesn't organize or manage the buffer memory 39?

[00:01:41] Speaker 02:
I do not agree with the board's conclusion on that, Your Honor.

[00:01:45] Speaker 02:
That's correct.

[00:01:46] Speaker 00:
And so that's an issue that we would review for substantial evidence, right?

[00:01:50] Speaker 02:
Correct.

[00:01:50] Speaker 02:
But again, we have to look at the facts to see whether the facts support that conclusion.

[00:01:55] Speaker 00:
Yeah, that's what I mean by substantial evidence, whether there's factual evidence to support that fact finding.

[00:02:01] Speaker 02:
Right.

[00:02:01] Speaker 02:
Yes, Your Honor.

[00:02:02] Speaker 02:
And if there's any device in the Joshi system that in fact controls, organizes, or manages to use the board's language, it's going to be RAM buffer controller 44.

[00:02:16] Speaker 02:
That's the one that sets the addresses to be read from or stored to.

[00:02:21] Speaker 02:
It dictates.

[00:02:22] Speaker 02:
what the buffer memory 38 does in terms of whether it's reading or writing, that's the device that's gonna be the closest to being something that controls the buffer memory 38.

[00:02:34] Speaker 02:
The data path controller, I'm sort of jumping ahead a little bit in my argument here, but the data path controller, the director argued, controlled the buffer memory 38, but what the reference actually says is it serves to control the data transmission to and from the buffer memory 38.

[00:02:53] Speaker 02:
That's at column 8, lines 52 to 55.

[00:02:55] Speaker 02:
So it's controlling the interface, the data interface with the buffer controller, buffer memory 38.

[00:03:04] Speaker 02:
It's not controlling it itself.

[00:03:05] Speaker 02:
That's really being done by, if anything, by RAM buffer controller 44.

[00:03:11] Speaker 02:
So that's another reason for why the board's conclusions are unsupported by the actual evidence of record runner.

[00:03:20] Speaker 02:
And then in addition,

[00:03:22] Speaker 02:
The reference makes it clear that the datapath controller, this is another example of why we know that the datapath controller is external to, not part of, buffer memory 38.

[00:03:34] Speaker 02:
It has to request access to buffer memory 38, and that's when the RAM buffer controller 44 has to arbitrate between the different parts of the system to determine who has priority to access the buffer memory.

[00:03:49] Speaker 02:
And so if it were, you know, integral with or considered to be internal to the buffer memory, it would not need to make that request.

[00:03:56] Speaker 02:
So again, another reason for another piece of that and supporting our position, frankly, that the board's position, their conclusion was wrong about what constituted the multi-queue storage device.

[00:04:13] Speaker 02:
The board was also incorrect with respect to the

[00:04:16] Speaker 02:
the limitation regarding the generation of an address request signal.

[00:04:22] Speaker 02:
And again, this is sort of the same point, but couched in a different way.

[00:04:26] Speaker 02:
The signals that the board relied upon for the address request signal are generated by the datapath controller 43.

[00:04:34] Speaker 02:
And so once we recognize that that is not a part of the Multi-Q storage device, then the board's conclusion that the Multi-Q storage device generates the address request signal is necessarily wrong as well.

[00:04:48] Speaker 00:
So your second argument that you're making here really rises and falls with whether the board erred in finding that the buffer memory, or that the buffer memory 39 combined with the data path controller 43 is multi-queue memory, right?

[00:05:05] Speaker 02:
That's right.

[00:05:06] Speaker 02:
It's just a logical conclusion based on my first argument.

[00:05:10] Speaker 02:
That's right, Your Honor.

[00:05:12] Speaker 02:
But the third argument I want to make is that

[00:05:15] Speaker 02:
the signals that in fact the board identified and relied upon as that address request signal are in fact not requesting an address.

[00:05:24] Speaker 02:
The board relied on the data path controller read request.

[00:05:28] Speaker 02:
There's an asynchronous and a synchronous version.

[00:05:31] Speaker 02:
The acronym was DRDREQS and DRDREQA.

[00:05:37] Speaker 02:
Those data path controller read request signals are requesting access to

[00:05:44] Speaker 02:
the buffer memory 38.

[00:05:45] Speaker 02:
They're not requesting an address and the claim is clear that the signal that's generated has to be requesting an address.

[00:05:55] Speaker 02:
That's right in the claim language.

[00:05:57] Speaker 02:
So it isn't requesting access to the buffer memory is not

[00:06:03] Speaker 02:
the same thing as requesting an address, which is what, of course, happens in the patent owner's patent.

[00:06:12] Speaker 02:
It's a different architecture, frankly.

[00:06:15] Speaker 02:
And so those address signals, and frankly, even the petitioner's expert, he testified that an address request signal requests a queue address.

[00:06:26] Speaker 02:
We have that site that's on APPX 1387, Your Honor.

[00:06:34] Speaker 02:
So the fact that there I know that the director has pointed to the fact that in the board frankly relied upon the fact that downstream of making that access request there is some address.

[00:06:48] Speaker 02:
It's one of many things that happens as a result of the datapath controller sending that access request to the RAM buffer controller.

[00:06:58] Speaker 02:
It's not requesting an address.

[00:07:00] Speaker 02:
Give me an address.

[00:07:01] Speaker 02:
What's the next address you want me to read from?

[00:07:03] Speaker 02:
It's saying I'd like to have access to the buffer memory.

[00:07:33] Speaker 01:
On the first issue with respect to the Multi-Q storage device and what constitutes that device, as Monterey's Council acknowledged, the Ford's construction is uncontested that

[00:07:48] Speaker 01:
that the control logic can be internal or external to the buffer memory itself.

[00:07:57] Speaker 01:
And so whether you want to draw a box around simply the buffer memory 38 or draw a box around both the buffer memory 38 and the datapath controller 43, you still have a device.

[00:08:16] Speaker 03:
The way I heard his argument, he's basically boiling it down to the requesting an address limitation.

[00:08:26] Speaker 03:
Isn't that what you understood him to be arguing essentially?

[00:08:29] Speaker 01:
He is arguing that as well.

[00:08:31] Speaker 03:
But not as well.

[00:08:32] Speaker 03:
I mean, that seems to be the heart of his argument here.

[00:08:36] Speaker 03:
What's your response to that?

[00:08:38] Speaker 03:
My response is that we look at- What teaches in Joshi the requesting an address?

[00:08:46] Speaker 01:
The data path controller 43 transmits the synchronous or the asynchronous request to the RAM buffer controller 44.

[00:08:55] Speaker 01:
The data path controller always has priority.

[00:09:00] Speaker 00:
Are you relying on the DRDEQS signal?

[00:09:06] Speaker 00:
Yes.

[00:09:07] Speaker 00:
Why is that an address request signal?

[00:09:10] Speaker 01:
Because that is what is

[00:09:14] Speaker 01:
ultimately causing the RAM buffer controller to send an address to the buffer memory 38.

[00:09:20] Speaker 01:
That is the purpose.

[00:09:21] Speaker 00:
Even if it's not saying it's an address request, what it gets back is an address, and therefore it's an address request?

[00:09:28] Speaker 01:
Yeah, I think the claim language address request is very broad.

[00:09:35] Speaker 01:
These figures we're looking at here... What's the consequences of the data problem?

[00:09:40] Speaker 03:
What's the consequence of it being brought?

[00:09:45] Speaker 01:
The consequences of it being brought is that when we're looking at Joshi, we don't need to

[00:09:55] Speaker 01:
So to take a step back, in both the 226 pattern and Joshi, these figures we're looking at are simply block diagrams that are showing conceptual relationships.

[00:10:07] Speaker 01:
And so these are not physical devices here in the figures that we're looking at.

[00:10:15] Speaker 01:
If the question is, is that does Joshi meet the requirement for an address request signal?

[00:10:24] Speaker 01:
The fact that the data path controller is initiating that signal to the RAM buffer controller, which then is... Is that requesting an address signal?

[00:10:38] Speaker 01:
I believe it is.

[00:10:39] Speaker 03:
I mean, that is why the... I'll say exactly what I mean.

[00:10:45] Speaker 01:
On page 910, and I'm sorry, Your Honor, you're asking for the prior art or for the claim languages?

[00:10:53] Speaker 01:
Well, the claim language of the patent under consideration here simply says, claim one said, multi-queue storage device is configured to generate an address request signal.

[00:11:09] Speaker 01:
And Joshi

[00:11:14] Speaker 01:
on pages 907 and 910 of the appendix explains how that works.

[00:11:34] Speaker 01:
I'm reading on column 10, appendix page 907, where starting at line 10, the RAM buffer controller includes

[00:11:44] Speaker 01:
request arbitration logic, which serves to arbitrate for the requests.

[00:11:50] Speaker 01:
And so what this is saying here is that the data path controller always has priority to go through, to send a request through the RAM buffer control.

[00:12:00] Speaker 01:
Then on page 910 of the appendix, column 15, line 49,

[00:12:11] Speaker 01:
When access to the medium is obtained, the datapath controller will assert a service request requesting that data be read from the buffer memory 38.

[00:12:20] Speaker 01:
The request from the datapath controller takes the form of assertion of the signal DRD

[00:12:29] Speaker 01:
request synchronous or DRD request asynchronous.

[00:12:33] Speaker 01:
The two signals stand for datapath controller read request synchronous and so on.

[00:12:40] Speaker 01:
So the assertion of a datapath controller read request causes the control logic to generate the proper select signal and then there is a pointer, the read pointer for the transmit buffer.

[00:12:55] Speaker 01:
So that pointer that we're ultimately getting is

[00:12:59] Speaker 04:
is an address.

[00:13:00] Speaker 01:
Correct.

[00:13:05] Speaker 01:
So when we compare what's going on in the 226 pattern that's under challenge here and we compare that to what Joshi is doing, it is at the end of the day the same thing.

[00:13:17] Speaker 01:
An address is requested and

[00:13:23] Speaker 01:
an address is generated sent to the multi-queue storage memory and that data that is at that address is produced.

[00:13:33] Speaker 00:
I think that what the Appellants Council is arguing here is one of the additional arguments that they're making is that this box drawing combining elements 43 and 38 is arbitrary, right?

[00:13:46] Speaker 00:
That there's no reason to combine those two together and in particular

[00:13:51] Speaker 00:
taking the view that this DPC 43 isn't actually controlling the buffer memory 38, right?

[00:14:00] Speaker 00:
It's only controlling the data on the path.

[00:14:02] Speaker 00:
What is your response to that?

[00:14:05] Speaker 01:
It is controlling the buffer memory.

[00:14:07] Speaker 01:
That is the element that is causing that address request to be initiated.

[00:14:18] Speaker 01:
That's why it's there.

[00:14:21] Speaker 00:
To me, that seems to be managing the... What would be the record sites that you would give for that point?

[00:14:28] Speaker 00:
Sure.

[00:14:32] Speaker 00:
I know there's column 8, lines 52 to 55, which your expert also cited, about how the datapath controller serves to control the data transmission to and from the buffer memory 38.

[00:14:45] Speaker 00:
Do you have anything in addition to that?

[00:14:48] Speaker 01:
That is our site for that, and we believe that that is substantial evidence.

[00:14:54] Speaker 00:
What about the fact that it says data transmission?

[00:14:56] Speaker 00:
Do you think that makes a difference?

[00:14:58] Speaker 00:
Do you think that controlling the data transmission should be understood as also controlling the memory?

[00:15:06] Speaker 01:
My understanding of controlling data transmission is that it's controlling data that is ultimately

[00:15:17] Speaker 01:
going out on the data bus to go somewhere else.

[00:15:19] Speaker 01:
And so I think conceptually, I think they're two different functions, but they are related, and I think it's plausible that the datapath controller can do both.

[00:15:31] Speaker 01:
It certainly doesn't detract from its ability to

[00:15:36] Speaker 01:
to initiate that address request signal.

[00:15:40] Speaker 00:
I was just going to that.

[00:15:40] Speaker 00:
I mean, I think they're relying on the board's construction that the logic or component that organizes or manages the queues can be internal or external.

[00:15:48] Speaker 00:
So how is it that the component 43 organizes or manages the queues?

[00:15:57] Speaker 01:
Well, what I believe is actually organizing and managing the queues is the RAM buffer controller.

[00:16:02] Speaker 01:
So really it's three elements we're looking at here that are working together.

[00:16:06] Speaker 01:
It's the data path controller, the RAM buffer controller, and the buffer memory.

[00:16:10] Speaker 01:
And it's that RAM buffer controller that's doing the managing.

[00:16:13] Speaker 01:
It's the same concept that we're looking at with the datapath controller and that they, when we're looking at these diagrams at such a level of abstraction that we can consider them all to be part of the same device.

[00:16:29] Speaker 00:
In other words, your argument doesn't depend on whether the datapath controller 43 controls the cues in the buffer memory, right?

[00:16:38] Speaker 01:
That's correct.

[00:16:39] Speaker 00:
Okay.

[00:16:40] Speaker 00:
Thank you.

[00:16:42] Speaker 04:
What is the affirmative justification for treating 43 and 38 together as a unit constituting the multi-key storage device?

[00:16:56] Speaker 01:
The affirmative argument is that functionally they perform the same thing as what the memory is doing in the 226 patent.

[00:17:08] Speaker 01:
an address request has to be generated and that is what prompts this loop of an address being pulled and then sent back to the button.

[00:17:20] Speaker 01:
So the same sequence of events are happening.

[00:17:23] Speaker 01:
In addition, because the diagrams we're looking at are block diagrams and are at a level of abstraction that would leave to the engineer the

[00:17:37] Speaker 01:
the choices to exactly what physical components to use when designing this system that what constitutes a device in the first place is very broad.

[00:18:01] Speaker 04:
Can I just ask a quick question about the second issue, about the request?

[00:18:10] Speaker 04:
Was there a claim construction for Patrick's request system?

[00:18:20] Speaker 01:
No, there was not.

[00:18:21] Speaker 01:
There was not an expressed claim construction.

[00:18:25] Speaker 04:
Or any requested?

[00:18:27] Speaker 01:
I don't believe there was.

[00:18:31] Speaker 04:
Is it your view that the board's decision depends on saying that if I make a request to you and in order for you to fulfill it, you need to get an address, then I have requested an address, even though I'm not particularly thinking about an address?

[00:18:53] Speaker 01:
I believe the board's view is that when, Judge Toronto, you're asking me

[00:18:59] Speaker 01:
that initial prompt is that we are assuming that an address is going to be requested.

[00:19:05] Speaker 01:
So that is the purpose of that communication being asserted.

[00:19:09] Speaker 04:
Because you can't get what I've requested without an address.

[00:19:18] Speaker 01:
Correct.

[00:19:20] Speaker 01:
But the, again, the

[00:19:25] Speaker 01:
The only reason you're asking me to do it is because we know that in address I'm going to go request one and then it's going to be sent to the buffer memory.

[00:19:43] Speaker 01:
I just wanted to provide one additional site.

[00:19:45] Speaker 01:
I mentioned that these are block diagrams that we're looking at at a pretty high level of abstraction.

[00:19:52] Speaker 01:
Page 53, appendix page 53, column 9, starting at line 33 discusses that and the 226 patent.

[00:20:08] Speaker 01:
If there are no further questions, I will yield the remainder of my time.

[00:20:25] Speaker 02:
Thank you, Your Honor.

[00:20:27] Speaker 02:
Just quickly, I'm going to pick up with the address request signal.

[00:20:32] Speaker 02:
Keep in mind the claim language is that the circuit has to generate an address request signal.

[00:20:36] Speaker 02:
It isn't enough that somewhere along the line in the system

[00:20:41] Speaker 02:
an address is served up.

[00:20:45] Speaker 02:
It has to generate an address request signal, and that is not being done here.

[00:20:51] Speaker 02:
Those signals are service request signals or access request signals, signals saying, I'm the DPC, I'd like to, in this case, read data from the buffer

[00:21:02] Speaker 02:
and then the RAM buffer controller 44 arbitrates and determines who has highest priority and gives that device.

[00:21:10] Speaker 04:
In your view in the Joshi system, does someone send out a request for an address?

[00:21:22] Speaker 02:
Actually, no.

[00:21:22] Speaker 02:
As it relates to the

[00:21:27] Speaker 02:
portion of Joshi that the board has relied upon.

[00:21:29] Speaker 02:
There isn't a request for an address at all.

[00:21:34] Speaker 04:
I take it your point is there isn't from the DPC.

[00:21:36] Speaker 04:
Is there from the RAM buffer controller a request for an address?

[00:21:41] Speaker 04:
No, Your Honor, there isn't.

[00:21:43] Speaker 04:
I thought in Joshi there's discussion of

[00:21:47] Speaker 04:
at least getting an RPX pointer, which Joshi says is an address.

[00:21:53] Speaker 02:
Nobody requests it?

[00:21:54] Speaker 02:
Nobody requests it.

[00:21:55] Speaker 02:
Nobody issues a command saying, send me the next address, or send me the address you'd like me to access.

[00:22:03] Speaker 02:
Instead, all that's generated is, from the datapath controller, a request that I'd like to access the buffer memory 38.

[00:22:11] Speaker 02:
That's sent to the RAM Buffer Controller 44.

[00:22:14] Speaker 02:
RAM Buffer Controller 44, the Joshi reference explains that when it receives that read request signal from the datapath controller, it does a number of things.

[00:22:25] Speaker 02:
It reconfigures multiple multiplexers within the circuitry.

[00:22:29] Speaker 02:
It sends signals as a result send signals to multiple areas of the circuit Including to the buffer memory one of those signals is to send an address to the buffer memory But it isn't requested by the date that specific One of the many things that the RAM buffer controller does is to

[00:22:53] Speaker 02:
Generate an address this pointer discussed earlier it generates it it generates the address itself Okay, but the address wasn't requested by the datapath controller all that the datapath controller generated Per the claim language was an access request signal.

[00:23:12] Speaker 02:
I need to access The buffer memory 38 and then from there.

[00:23:16] Speaker 02:
There's this there's this whole discussion.

[00:23:17] Speaker 03:
I think it's

[00:23:19] Speaker 03:
I'm sorry.

[00:23:20] Speaker 03:
You say it generates an address, written number 44.

[00:23:24] Speaker 03:
Yes.

[00:23:24] Speaker 03:
What address to what?

[00:23:27] Speaker 02:
In the case of the read request, the signals we're talking about, it generates an address to the buffer memory 38 telling... What to read?

[00:23:38] Speaker 02:
Telling the buffer memory 38 what location to output the data from.

[00:23:43] Speaker 03:
So it says... What address to pick?

[00:23:47] Speaker 02:
based on the address sent from RAM buffer controller 44.

[00:23:50] Speaker 02:
I'm sorry.

[00:23:55] Speaker 03:
But you say it's written 44 that generates the address.

[00:23:58] Speaker 02:
It generates, but those are, that's right, it generates.

[00:24:01] Speaker 03:
It generates it from what?

[00:24:02] Speaker 03:
How does it know the address is going to go someplace where something is stored in the memory of the general read, right?

[00:24:07] Speaker 02:
That's right.

[00:24:08] Speaker 03:
That's right, Your Honor.

[00:24:09] Speaker 03:
And so that's where, without the address, you can never find what to read.

[00:24:13] Speaker 03:
That's right, Your Honor.

[00:24:19] Speaker 03:
know what to generate.

[00:24:20] Speaker 02:
Okay, and this is not really addressed in the board's decision, but Joshi explains that node processor 52, so the block that's on the far left, it initiates all of these devices, 44, 43, and 34 in particular, using that bus up at the top labeled NPI.

[00:24:40] Speaker 02:
that bus, that node processor bus, it uses those who initiate that.

[00:24:45] Speaker 02:
Part of the initiation process is to set up these, what the board called, multiple queues, multiple FIFOs, first in, first out memory configurations within the buffer.

[00:24:56] Speaker 02:
And so what it does is it initializes the RAM buffer controller with an address to start with for each of those FIFOs.

[00:25:04] Speaker 03:
Configure to generate an address is what we're worried about.

[00:25:08] Speaker 03:
That's right.

[00:25:09] Speaker 04:
I'm sorry, a request for an address.

[00:25:15] Speaker 02:
And that is the key distinction, Your Honor.

[00:25:19] Speaker 02:
It's request to generate an address.

[00:25:23] Speaker 02:
It's not the generation of an address that satisfies the claim language.

[00:25:28] Speaker 02:
The claim language says it has to be configured to generate an address request.

[00:25:39] Speaker 02:
That's right.

[00:25:39] Speaker 02:
And in particular, we're looking at the board's conclusion.

[00:25:43] Speaker 02:
And they relied on two particular signals that I read into the record.

[00:25:48] Speaker 03:
But the request signal, the thing that's being sent by 44 someplace to read is a signal, right?

[00:25:55] Speaker 02:
It is.

[00:25:55] Speaker 02:
Yeah, it's an address signal.

[00:25:57] Speaker 02:
It's on this address bus.

[00:25:59] Speaker 02:
So 44 is generating an address.

[00:26:03] Speaker 03:
But it's in form of signal.

[00:26:10] Speaker 03:
information has to read, right?

[00:26:12] Speaker 03:
Yeah.

[00:26:13] Speaker 03:
It doesn't get read without a signal coming from forward to where the doctor works told.

[00:26:19] Speaker 02:
I agree, Your Honor.

[00:26:20] Speaker 03:
So there isn't... Is that generating a request for a signal?

[00:26:26] Speaker 02:
No, it's... Well, the claim language is... You just read it so I'm being specific.

[00:26:32] Speaker 02:
So the claim language is that the multi-queue storage device, so

[00:26:37] Speaker 02:
38 or 43, as identified by the board, one of those two has to generate an address request signal.

[00:26:47] Speaker 02:
What you're focusing on, your honor, is the address itself, that in the 226 patent is returned in response to the address request signal.

[00:26:58] Speaker 02:
So in the 226 patent, the memory, the multi-queue storage device, requests an address.

[00:27:06] Speaker 02:
And then the interface, in response, sends the address.

[00:27:10] Speaker 02:
And what you're most closely looking at, Your Honor, is what would be in the 226 patent, the response to the address request signal.

[00:27:18] Speaker 03:
But the claim language is generating the address request signal itself, not... Does it sound just beautiful when all this happens directly or indirectly?

[00:27:31] Speaker 02:
I think that goes to the... It was external or internal.

[00:27:34] Speaker 02:
I believe, Your Honor.

[00:27:36] Speaker 02:
If I'm... Maybe I'm missing your point, Your Honor.

[00:27:38] Speaker 00:
Can I ask you another question?

[00:27:39] Speaker 00:
When the signal, D-R-D-R-E-Q-S, is sent to the RAM buffer controller 44, there is some disclosure that things happen and then an address

[00:27:52] Speaker 00:
is request is sent to buffer memory 38.

[00:27:56] Speaker 00:
What are the things besides an address request are disclosed to have been sent in response to the DRD, I just want to make sure I got it right, DRD-REQS signal.

[00:28:08] Speaker 02:
So just to clarify

[00:28:09] Speaker 02:
an address is sent from 44 to 38.

[00:28:11] Speaker 02:
I think you said an address.

[00:28:13] Speaker 00:
Yeah, that's what I meant.

[00:28:14] Speaker 00:
You're right.

[00:28:14] Speaker 00:
You're right.

[00:28:15] Speaker 00:
An address.

[00:28:16] Speaker 00:
And what other things would be done in response?

[00:28:19] Speaker 00:
I mean, you're saying that the DRD-REQS isn't an address request signal.

[00:28:23] Speaker 00:
The response is, well, what happens in response to receiving that is an address is sent to buffer memory 38.

[00:28:31] Speaker 00:
And so I'm wondering, what else are you contending would happen in response to the sending of the DRD-REQS?

[00:28:37] Speaker 02:
I understand, Your Honor.

[00:28:39] Speaker 02:
So I don't have the APPX number.

[00:28:41] Speaker 02:
I'm sorry.

[00:28:42] Speaker 02:
A copy of the Joshi reference I have doesn't have those numbers on it.

[00:28:45] Speaker 02:
But it's at columns 15 and 16.

[00:28:49] Speaker 02:
And in particular, it begins roughly at column 15, line 49, it looks like.

[00:28:54] Speaker 02:
And it goes over to column 16, roughly line 9.

[00:28:59] Speaker 02:
And that's what I think.

[00:29:00] Speaker 00:
That's about what I'm looking at, to be honest with you.

[00:29:03] Speaker 00:
We're focused on the same part of the spec.

[00:29:05] Speaker 00:
And what I see happening here is that in response to the sending of the DREQS signal, there is an address that is sent to the buffer.

[00:29:18] Speaker 02:
There is.

[00:29:19] Speaker 02:
There is, Your Honor.

[00:29:20] Speaker 02:
I'm not disputing that an address isn't, in fact, sent.

[00:29:23] Speaker 02:
But I'm simply saying that the signal that's sent from the datapath controller 43 is not requesting an address.

[00:29:30] Speaker 02:
It's saying, I want to have access to the RAM buffer controller.

[00:29:34] Speaker 02:
And again, the board doesn't.

[00:29:36] Speaker 02:
Can I just interrupt?

[00:29:37] Speaker 04:
Because I know you're over time already.

[00:29:39] Speaker 04:
But if 43 and 38 were treated as a single unit, which is, I think, the first issue that you're

[00:29:53] Speaker 04:
for itself an address.

[00:29:57] Speaker 02:
Okay, and as you know, we don't agree with the idea that the two should be treated together.

[00:30:01] Speaker 04:
But I wonder if we disagree with you about the first point, then we need to treat the datapath controller and the buffer memory as a single unit.

[00:30:11] Speaker 04:
That unit sends out a request and gets back an address, a necessary part of

[00:30:24] Speaker 04:
I want information.

[00:30:26] Speaker 02:
I think, first of all, the words in the claim have to have meaning.

[00:30:30] Speaker 02:
It can't just be any signal that's sent out that returns an address.

[00:30:35] Speaker 02:
In fact, the claim doesn't even require that an address be returned.

[00:30:38] Speaker 02:
It's requesting an address.

[00:30:40] Speaker 04:
But any request for stored data necessarily encompasses an identification of a location where to find it.

[00:30:50] Speaker 02:
In the context of the 226 patent, I think that's true, Your Honor.

[00:30:55] Speaker 02:
And I think that in this portion of the specification that I was discussing with Judge Stoll, it explains there's a lot of reconfiguration that occurs within the RAM buffer controller 44 itself, which is shown in detail in other figures, like figures two and I think it's figures four.

[00:31:13] Speaker 02:
There are two different views of all the circuitry within that RAM buffer controller 44.

[00:31:18] Speaker 02:
And a lot of steps take place, and those are described, some of which at least,

[00:31:23] Speaker 02:
are described in this column 15 to column 16 citation that I gave.

[00:31:27] Speaker 02:
But it's not requesting an address.

[00:31:28] Speaker 02:
It's saying, I would like to have access to the RAM buffer controller.

[00:31:32] Speaker 02:
The node processor, 52.

[00:31:34] Speaker 02:
I think we actually know.

[00:31:36] Speaker 02:
You get it?