[00:00:00] Speaker 03: Our first argued case is Bell Semiconductor versus NXP et al., 2023-1260. [00:00:09] Speaker 03: Mr. Silver. [00:00:10] Speaker 03: Good morning, Your Honors. [00:00:14] Speaker 00: May it please the Court, Blair Silver, on behalf of Appellant Bell Semiconductor. [00:00:19] Speaker 00: In this case, the Board's obviousness decision cannot stand because the Board failed to follow clear Supreme Court precedent that requires defining [00:00:28] Speaker 00: a clear starting point when evaluating the prior art reference chin for single reference obviousness. [00:00:36] Speaker 00: Evaluate that reference as a whole, identify the differences, and then find a motivation to depart from chin. [00:00:42] Speaker 00: In addition, the board also aired in its analysis of the parasitic capacitance reduction limitation that requires a reduction between two specifically described claim layers in the 3-4-0 pattern by resting on an incomplete [00:00:57] Speaker 00: And more importantly, an unargued inherency finding that NXP has now expressly disavowed in its briefing. [00:01:03] Speaker 00: Now I'll focus my remarks today on claim one. [00:01:05] Speaker 00: If the court has any questions about claims 16 and 17 that are also in our brief, please feel free to ask. [00:01:11] Speaker 00: Now on the first issue, the board did not grapple with Chin, the main and only reference, against claim one as a whole. [00:01:18] Speaker 00: Now there's no dispute on the law in this case. [00:01:21] Speaker 00: References must be read as a whole, even the parts that teach away. [00:01:25] Speaker 00: References require a starting point to comply with Graham, where you identify claim differences. [00:01:31] Speaker 00: And then you need a motivation to meet those claim differences. [00:01:34] Speaker 00: And as Westlaw teaches, you cannot pick and choose out of context parts from the specification. [00:01:40] Speaker 00: But that's exactly what the board did here. [00:01:43] Speaker 00: NSP's changing starting point embodies this problem. [00:01:47] Speaker 00: When the board was deciding this case before, it was Chin alone. [00:01:51] Speaker 00: That was abundantly clear in the briefing. [00:01:54] Speaker 00: By the time we get on appeal, and this is probably emblematic of Chin's lack of teaching of integrated circuit package substrates, it's now an integrated circuit package substrate that's a typical integrated circuit package substrate being modified by Chin. [00:02:09] Speaker 00: Moreover, the board in this case had trouble even determining whether there was this parasitic capacitance reduction in Chin, because it could not find a starting point for which to evaluate that. [00:02:17] Speaker 00: But here, Chin as a whole describes a printed circuit board with surface traces and pads, underlying reference planes with cutouts and compensation capacitors that fix a known impedance mismatch in Chin. [00:02:32] Speaker 00: Starting with that point, the board needed to identify the differences and find them on motivation. [00:02:38] Speaker 00: And those differences on appeal are the integrated circuit packet substrate and the parasitic capacitance reduction between the claim layers that we'll talk about in a minute. [00:02:46] Speaker 03: Mr. Silver, of course, what a reference teaches is question of fact. [00:02:50] Speaker 03: And so you've got a substantial evidence burden to overcome here. [00:02:57] Speaker 00: Well, Your Honor, traditionally, yes, that is the standard review for what a reference does teach. [00:03:01] Speaker 00: In this circumstance, though, the board's analysis disembodied of the reference was flawed because they failed to actually identify the starting point to compare the reference to the claims. [00:03:10] Speaker 00: So yes, while the actual reference teachings is a question of fact, the legal question of what is the framework for obviousness and how you comply with Graham is a legal question that the court can look at de novo. [00:03:21] Speaker 00: Now here, you need look no farther than the NXP's response brief. [00:03:26] Speaker 00: to see how weak the disclosure on integrated circuit package substrate is, where they seem to admit tacitly that Chin doesn't describe it because they modified their ground to now be a typical IC package substrate that is then modified by Chin. [00:03:39] Speaker 00: They wouldn't need to do so if Chin had a clear disclosure of integrated circuit package substrate. [00:03:43] Speaker 02: So you argue that there is a mismatch between Chin and the asserted claim. [00:03:51] Speaker 00: There's an impedance mismatch in Chin in terms of what the problem is solving. [00:03:56] Speaker 00: There's a mismatch. [00:03:57] Speaker 00: But there's also, the claims don't line up because Chin doesn't disclose an integrated circuit package. [00:04:01] Speaker 02: But isn't that the case in all situations where you're looking at obviousness? [00:04:06] Speaker 00: Absolutely not. [00:04:06] Speaker 02: I mean, if they did match up, then we'd have anticipation. [00:04:10] Speaker 00: And we do not have anticipation in this case. [00:04:12] Speaker 00: And this is a limitation where they were arguing obviousness. [00:04:15] Speaker 00: And so here we know that something is missing, and the board needed to bridge that gap to find the integrated circuit package substrate. [00:04:22] Speaker 00: And here the only thing the board latched onto, and that NXP mentions briefly on appeal, are individual words of the word substrate and semiconductor implementations plucked out of context from the brief. [00:04:33] Speaker 00: And as we explained in our briefing, each of those circumstances was indisputably talking about the printed circuit board side of a ball grid array. [00:04:41] Speaker 00: You're talking about the larger, [00:04:43] Speaker 00: Motherboard looking device not the small integrated circuit on top and there's been no dispute about that in their briefing that those Those mentions of semiconductors as mentions of substrates were all talking about the PCB side of a ball grid right now the board Dismissed the impedance matching goal of chin as not germane to its inclusion [00:05:03] Speaker 00: The board misread that case law. [00:05:06] Speaker 00: That case law was talking about whether the prior art for novices needed the exact same motivation. [00:05:12] Speaker 00: Here we're talking about modifying chin away from its core purpose of impedance matching. [00:05:17] Speaker 00: And there's no dispute that that is the core purpose of chin, is to match impedance between a surface microstrip and a pad. [00:05:25] Speaker 00: Now the board and NXP have not given any reason why [00:05:28] Speaker 00: you would ignore that goal, in fact, contrary that goal in the proposed modification to Chin. [00:05:35] Speaker 00: And there's no dispute in this case that if you were to add cutouts, underlying cutouts, in a system that doesn't have an impedance problem, you would actually cause an impedance problem. [00:05:45] Speaker 00: And there's no dispute in this case that Chin criticizes using cutouts in reference plans alone. [00:05:51] Speaker 00: And the law is clear, and again, undisputed, that you cannot change the basic principles of operation of a reference in obviousness, and you cannot modify away from a key feature without a concrete reason why, a motivation. [00:06:04] Speaker 00: And here, the board identified none. [00:06:07] Speaker 00: Now, I'd like to turn, unless the court has any questions about that first module, to the inherency argument with regard to the three-for-oh patent. [00:06:16] Speaker 00: This argument is independent of the single reference obviousness argument I just mentioned. [00:06:20] Speaker 00: The 340 pad requires that the cutouts reduce parasitic capacitance between two specifically claimed layers. [00:06:28] Speaker 00: There is no dispute in this case that Chin does not say that. [00:06:31] Speaker 00: Chin talks about reducing parasitic capacitance at the pad. [00:06:37] Speaker 00: You can see this in figure 2a of Chin. [00:06:40] Speaker 00: Element 220 is the pad. [00:06:42] Speaker 00: It's a square. [00:06:43] Speaker 00: It's a component in the middle of the surface. [00:06:46] Speaker 00: Layer 200 is the broader area in Chin that includes the traces [00:06:50] Speaker 00: and the compensation capacitors and other elements that would be present on that. [00:06:56] Speaker 00: NXP has conceded abundantly clear in its briefing that it did not argue inherency in the disclosure. [00:07:03] Speaker 00: NXP has conceded the board didn't find inherency. [00:07:06] Speaker 00: That's because NXP never raised inherency. [00:07:08] Speaker 00: So at this point, the board cannot make an inherency finding. [00:07:12] Speaker 00: Indeed, the board's only support for the physics involved between the two claimed layers was from one paragraph in their expert's background statement. [00:07:22] Speaker 00: And it's abundantly clear in the law that an expert's single paragraph in a background statement is not preserving an argument for appeal. [00:07:30] Speaker 00: It certainly was never applied to Chin in this case by any party. [00:07:34] Speaker 00: And therefore, what you have is a reference that does not teach something, no inherency, and no obvious argument to go along with it. [00:07:41] Speaker 00: And so there's no basis, there's no substantial evidence to affirm the board's decision with regard to the inherent disclosure. [00:07:48] Speaker 00: And moreover, the only evidence of record is actually that the capacitance between the layers is not known. [00:07:54] Speaker 00: And in fact, could be greater than before you do Chin's method. [00:07:58] Speaker 00: And that's undisputed on appeal. [00:08:02] Speaker 00: Your Honor, I would like to briefly touch on claims 16 and 17, because I think I have a minute. [00:08:07] Speaker 00: On claims 16 and 17, claim two requires a second electrically conductive layer that is a routing layer. [00:08:14] Speaker 00: The board found that this claim was not shown to be unpatentable. [00:08:18] Speaker 00: And it did so because NXP has failed to provide a motivation to change Chin's undisputed second layer from a reference plane to a signal plane. [00:08:29] Speaker 00: Now in their briefing before the board, NXP, for claim 16, pointed back to claim 2 without analysis to say, see claim 2. [00:08:41] Speaker 00: Once they tied those claims together, the board could not come to an inconsistent result, because there's no separate argument to evaluate for that inconsistent result. [00:08:51] Speaker 00: In effect, claim 2 became representative of claim 16. [00:08:55] Speaker 00: Moreover, [00:08:57] Speaker 00: There was no dispute that Ching doesn't disclose this second reference plane, so a second layer as a signal plane instead of a reference plane. [00:09:07] Speaker 00: Claim 16 requires the adjacent electrically conductive planes mentioned in claim 12 to be signal planes. [00:09:16] Speaker 00: They require them under the serial data stream limitation in claim 16. [00:09:23] Speaker 00: Because they're tied together and because there's no argument of that, claim 16 is even farther away than claim 2 was. [00:09:32] Speaker 00: And because there was no motivation in the record to convert the second layer to a signal layer, there's no basis for the board to have found that those claims were unpatentable. [00:09:44] Speaker 00: Now, if the court has any further questions on any of those issues, I'd like to reserve the remainder of my time for rebuttal. [00:09:49] Speaker 03: We'll hold it for you. [00:09:56] Speaker 03: Mr. Clinton. [00:10:08] Speaker 01: Good morning, Your Honors, and may it please the Court. [00:10:11] Speaker 01: My friend indeed raised a number of arguments that were addressing factual determinations by the board which were reviewed for substantial evidence. [00:10:20] Speaker 01: These arguments should be denied because the board did make factual determinations [00:10:25] Speaker 01: with citations of the evidence and then explained their rationale. [00:10:29] Speaker 01: Bell is effectively asking this court to readway the evidence, which it does not do on appeal. [00:10:34] Speaker 01: So let's take a look at the, I want to address the points that were raised here particularly. [00:10:39] Speaker 01: Let's look at the integrated circuit, sorry, integrated circuit package substrate. [00:10:46] Speaker 01: Okay, Bell argues that Chin only discloses a printed circuit board or PCB implementation or embodiment. [00:10:52] Speaker 01: And in fact, Chin does describe an embodiment as a printed circuit board. [00:10:56] Speaker 01: He uses those words very carefully. [00:10:58] Speaker 01: However, the board disagreed that this is the only teaching of Chin. [00:11:02] Speaker 01: The board found that Chin actually expressly discloses an IC package substrate. [00:11:07] Speaker 01: Appendix 20, citing to Chin 1, 61 to 62. [00:11:11] Speaker 01: Specifically, Chin describes a substrate used inside a BGA package. [00:11:18] Speaker 01: A BGA package is exactly the same type of IC package substrate [00:11:22] Speaker 01: that the 340 patent and the 269 patent are talking about. [00:11:26] Speaker 02: The board went further and found that Chin expresses... Chin discloses the use of cutouts. [00:11:33] Speaker 01: So Chin, yes, Chin discloses the use of cutouts and it discloses an IC package thumb straight. [00:11:38] Speaker 02: Does it matter what size those cutups are? [00:11:41] Speaker 01: Does it matter what size they are? [00:11:42] Speaker 01: Right. [00:11:43] Speaker 01: It does matter. [00:11:44] Speaker 02: Does Chin require them to be a certain size? [00:11:47] Speaker 01: Chin does not require them to be any particular size. [00:11:51] Speaker 01: The board expressly found that Chen, in its disclosure, suggests and teaches the use of its cutouts and its design in an IC package substrate. [00:12:02] Speaker 01: The board quotes the present invention relates generally to the design and fabrication of printed circuits and multilayered substrates. [00:12:10] Speaker 01: Now, those are different. [00:12:11] Speaker 01: The multilayered substrate is a broader class of things than a printed circuit board. [00:12:17] Speaker 01: And we'll see in another example later that Chen was very careful with his language. [00:12:22] Speaker 01: And again, Chin also describes another example. [00:12:24] Speaker 01: It's talking about examples or applications of its technology in the background section. [00:12:30] Speaker 01: And it says, another example is a substrate used inside a BGA package. [00:12:34] Speaker 01: That's a Chin 56 to 65 cited by the board of Appendix 22. [00:12:41] Speaker 01: So there's substantial evidence. [00:12:43] Speaker 01: If there's a chance that there are two different interpretations of Chin, that satisfies substantial evidence if they picked one and explained why. [00:12:55] Speaker 01: OK. [00:12:55] Speaker 01: Bell also argues that the board ignored the other features of Chin and its goal. [00:13:03] Speaker 01: The teachings of Chin are not limited to the structure of its preferred embodiment. [00:13:07] Speaker 01: Netflix and Lear make that very clear. [00:13:10] Speaker 01: Further, the board actually addressed those additional features. [00:13:12] Speaker 01: So the features that my friend brought up were microstrips and tuning capacitors. [00:13:18] Speaker 01: OK. [00:13:19] Speaker 01: First, the board found that Chin does not require microstrips. [00:13:22] Speaker 01: This finding is based on substantial evidence, including Chen. [00:13:25] Speaker 01: Specifically, Chen talks about micro-strips as one embodiment. [00:13:28] Speaker 01: But it also talks about interconnecting traces. [00:13:31] Speaker 01: Again, a broader term. [00:13:32] Speaker 01: Chen's very clear when he wants to differentiate between something specific and something broad. [00:13:38] Speaker 01: So the board found that micro-strips were not required. [00:13:44] Speaker 01: And Dr. Bauer, who is Bell's expert [00:13:48] Speaker 01: Admitted that in an ic package substrate micro strips and other tuned impedance Lines were not necessary because they're very small and the speeds were less than four gigahertz the the ones that dr. Bauer were was familiar with and so Micro strips in particular that particular type of line was not required now my friend talked about micro strips he's making a point of micro strips because I [00:14:12] Speaker 01: He's saying Dr. Byers says that they're not in an IC package substrate. [00:14:16] Speaker 01: But Chen is not limiting his disclosure to that particular problem, microstrips on a PCB. [00:14:22] Speaker 01: He says that the problem, and again, that's in that background of the invention section, is the large pads versus the smaller interconnecting traces, is the phrase that Chen uses. [00:14:36] Speaker 01: That causes an impedance mismatch, which he's trying to address. [00:14:41] Speaker 01: OK. [00:14:42] Speaker 01: And then Bell argues that the board erred by ignoring the purpose of Chin. [00:14:45] Speaker 01: Again, the purpose was misstated. [00:14:48] Speaker 01: This argument was forfeited as well. [00:14:51] Speaker 01: And the stated purpose of Chin does not limit that disclosure. [00:14:56] Speaker 02: OK. [00:14:57] Speaker 02: Go back to what you were saying. [00:14:58] Speaker 02: What did you say is the purpose? [00:15:01] Speaker 02: Chin disclosed the purpose of the microscripts. [00:15:04] Speaker 02: Is it to address impedance or to cause it? [00:15:08] Speaker 02: Does it cause the impedance? [00:15:10] Speaker 02: Chin. [00:15:11] Speaker 02: Does it address it? [00:15:14] Speaker 01: So Chen observed a problem where you have this impedance mismatch when you have a large pad and a thin interconnecting trace. [00:15:22] Speaker 01: And so Chen observed this and said, OK, let's solve this problem. [00:15:26] Speaker 01: Along the way, Chen observed that, hey, in the prior art, people would cut out this metal beneath to reduce the parasitic capacitance. [00:15:34] Speaker 01: And then Chen discloses this additional fine tuning. [00:15:38] Speaker 01: That's the word that Bell uses in its brief. [00:15:40] Speaker 01: This fine tuning to add just a little bit back in to really match the impedance of the line. [00:15:46] Speaker 01: But Chen discloses both. [00:15:48] Speaker 01: The problem being solved that he's observed is an impedance mismatch between the large pad and a thin interconnecting trace. [00:15:56] Speaker 01: And then he's trying to solve that with this capacitance reduction. [00:16:01] Speaker 01: And then Chen offers a fine tuning option as well. [00:16:10] Speaker 01: OK, my friend brought up the issue of capacitance, whether or not there was a disclosure of the reduction of capacitance. [00:16:21] Speaker 01: The board found, so first of all, the board properly construed the phrase cutouts for reducing parasitic capacitance. [00:16:28] Speaker 01: between the pad layer and the second layer. [00:16:31] Speaker 01: My friend has used a couple of different, in the briefing in today, has used a couple different types of capacitance. [00:16:36] Speaker 01: He talks about parasitic capacitance. [00:16:38] Speaker 01: That's in the claim. [00:16:39] Speaker 01: And then he talks about capacitance, overall capacitance. [00:16:43] Speaker 01: And the claims speak nothing about overall capacitance. [00:16:46] Speaker 01: It's just talking about parasitic capacitance between that pad and the layers below it. [00:16:52] Speaker 01: The board relied on substantial evidence to determine that Chin's cutouts were disclosed to reduce parasitic capacitance and were successful. [00:17:01] Speaker 01: In particular, in appendix 36 to 37, it cites the Chin's experiment where Chin [00:17:08] Speaker 01: built a mock-up, I guess, of his design, ran it, and determined that it not only maps the impedance, but he also reduced the excess capacitance, another phrase for parasitic capacitance, and was able to achieve speeds of four to seven gigahertz, which is way, way faster than what the 340 patent is talking about. [00:17:30] Speaker 01: So there's substantial evidence that capacitance was reduced, parasitic capacitance. [00:17:36] Speaker 01: I'm sorry, I need to be precise. [00:17:37] Speaker 01: Parasitic capacitance was reduced in that example. [00:17:41] Speaker 01: OK. [00:17:42] Speaker 01: My friend also talks about claims 16 and 17 rising and falling with claim 2. [00:17:47] Speaker 01: The board correctly recognized NXP's, excuse me, NXP only cited to a portion of claim 2. [00:17:54] Speaker 01: And the board correctly recognized that NXP was only referencing claim 2 for its commensurate limitations in claim 2. [00:18:01] Speaker 01: That's in appendix 68. [00:18:04] Speaker 02: Is that because claim two turns on the routing placement limitation and claims 16 and 17 don't have that limitation? [00:18:13] Speaker 01: That's the reason the claim two was found not invalid, whereas 16 and 17 were. [00:18:19] Speaker 01: Because that part of claim two, the board, disagreed with the petition and did not find the routing layer limitation. [00:18:28] Speaker ?: OK. [00:18:29] Speaker 01: Are there other questions about the appeal part? [00:18:32] Speaker 01: All right. [00:18:32] Speaker 01: So let me turn to the cross appeal. [00:18:34] Speaker 01: So NXP raises two points of error. [00:18:36] Speaker 01: First, the board erred by misapplying the law of obviousness regarding same size limitation. [00:18:42] Speaker 01: The court's decision in valiant provides clear guidance. [00:18:46] Speaker 01: So in that case, the prior art disclosed a pH range of three to seven, and the claim required three to four. [00:18:55] Speaker 01: District court found, well, that's not a finite set of options that might have been obvious to try. [00:19:00] Speaker 01: Mathematically, that's an infinite range. [00:19:03] Speaker 01: There are an infinite number of options in there. [00:19:05] Speaker 01: This court disagreed and said the mathematical approach is not how this should be considered. [00:19:11] Speaker 01: What we should consider is, in reality, personal awareness field in the art is going to select from [00:19:16] Speaker 01: a finite set of options within that. [00:19:18] Speaker 01: Maybe it's tens of options, maybe it's hundreds of options, but it's going to be a finite set of options rather than some mathematically infinite. [00:19:26] Speaker 01: And that makes sense because somebody's going to go dial in a particular size, and that's how they're going to test these out. [00:19:34] Speaker 01: Similar to the Defendant Invalient, NXP explained to the board that there are three options for size and cutouts. [00:19:39] Speaker 01: There's smaller, so undersized, there's same size, and there's oversized. [00:19:45] Speaker 01: And this was in Appendix 54, a side of the hearing in the briefing. [00:19:51] Speaker 01: And then this was clear in our petition at Appendix 348 and 6181. [00:19:55] Speaker 01: OK, no party suggested undersized is something that Pasita would be interested in, because you're not fully eliminating the parasitic capacitance, which is something that Chin was talking about. [00:20:06] Speaker 01: OK, so let me skip over the same size for a second and talk about oversized. [00:20:12] Speaker 01: So in the record, oversized cutouts [00:20:16] Speaker 01: are primarily used by Chen to address some manufacturing alignment issues with a particular process that he was using. [00:20:23] Speaker 01: So he oversized the cutouts so that everything would align, and then reintroduced some parasitic capacitance to do some fine tuning afterward. [00:20:37] Speaker 01: Chen also says in that process that by oversizing them [00:20:41] Speaker 01: you might be introducing some impedance mismatch, kind of right there in that void where it's a little bit oversized. [00:20:49] Speaker 01: You might get a little additional impedance at that point. [00:20:51] Speaker 01: And so cautious against that. [00:20:53] Speaker 01: And again, that's part of why the cutouts there help tune that in. [00:20:57] Speaker 01: OK, so this leaves. [00:21:01] Speaker 01: OK, so then we look at that oversized cutout range. [00:21:04] Speaker 01: Again, it's not an infinite range like the board found. [00:21:07] Speaker 01: This court says we should look at that [00:21:10] Speaker 01: It's a set of finite options within that range. [00:21:12] Speaker 01: And truly, you're limited. [00:21:13] Speaker 01: If you look at Graybrief at 9, you can see that because these are repeating pads, you can only oversize so much because you're going to need to walk into the other pads. [00:21:25] Speaker 01: OK, so this leads us to the most obvious third option, the same size. [00:21:29] Speaker 01: If you pick the same size option, then you completely reduce or completely eliminate the parasitic capacitance. [00:21:35] Speaker 01: And you don't introduce the problem that Chen was [00:21:39] Speaker 01: potentially concerned about with that mismatch. [00:21:42] Speaker 01: So much like Invaliant, the realistic size options are properly treated as limited options, and remand would be appropriate to allow the board to consider under the proper standard. [00:21:52] Speaker 01: Okay, the second point, the board aired by not allowing briefing under the construction of routing layer. [00:21:59] Speaker 01: So the board, in its final written decision, construed the term routing layer without any opportunity for the parties to address that construction. [00:22:07] Speaker 01: The board recognized that the term routing layer was not clear, but it was clear enough that it construed the term to mean a layer including at least one routing trace, or at least a routing trace, is the specific language at appendix 45 and 115. [00:22:22] Speaker 01: Because the parties were not afforded an opportunity to brief under that adopted construction, [00:22:31] Speaker 01: The board discussed whether NXP had proved that they would swap the routing layer of Chin with the reference layer. [00:22:38] Speaker 01: Just replace them, swap them. [00:22:40] Speaker 01: And that's not required under that construction. [00:22:42] Speaker 01: All we need to show is one routing trace on that second layer. [00:22:46] Speaker 03: Council, you wanted to save a little time to respond on the cross appeal if it's dealt with. [00:22:53] Speaker 03: It's up to you. [00:22:54] Speaker 01: Thank you. [00:22:54] Speaker 01: I just one more point, or a couple more points, and then I'll reserve my time. [00:22:58] Speaker 01: Thank you. [00:23:01] Speaker 01: In this case, the boar also found, or yes, it found in appendix 41 and 43, that a posita would likely have needed to add routing traces to that second layer. [00:23:10] Speaker 03: Who would? [00:23:11] Speaker 01: The posita would. [00:23:13] Speaker 01: the board determined the person of ordinary skill, speaking English rather than acronyms, would have likely needed to add routing traces. [00:23:24] Speaker 01: And this was the position we had taken in the petition, that it would have been likely necessary to add a route through that second layer, just with the number of signals going through. [00:23:35] Speaker 01: This would have meant that that first layer of chin, as modified by what the person of ordinary skill would have needed to do, [00:23:43] Speaker 01: That layer would have become both a routing layer and a reference layer. [00:23:48] Speaker 01: And this is consistent with what the 340 pattern figure 3 discloses, which is a mix of routing and reference planes. [00:23:57] Speaker 01: And in fact, Bell's expert admitted that a layer could be a little bit of both. [00:24:01] Speaker 01: And so remand is appropriate to address these facts under the board's new construction. [00:24:06] Speaker 01: And I'll reserve the rest of my time. [00:24:08] Speaker 03: We'll save it for you. [00:24:10] Speaker 03: Mr. Silver. [00:24:18] Speaker 00: Thank you, Your Honor. [00:24:20] Speaker 00: The word integrated circuit does not appear anywhere in Chin. [00:24:25] Speaker 00: And we explained in our brief how those snippets of words that say substrate, that say semiconductor implementation, they're taken out of context by the board. [00:24:35] Speaker 00: And so when you read the full paragraph surrounding them, what you will find is in every instance, and you didn't hear my friend on the other side say this, they're talking about the printed circuit board and when it interfaces with those components, or they're just talking about printed circuit boards in general. [00:24:49] Speaker 00: The one example that my colleague on their side gave was the statement, another example is a substrate used inside a BGA package in column one of CHIM. [00:25:01] Speaker 00: Reading the sentences preceding that and following that, it's talking about the solder ball that's attached to those, and when that gets added to the printed circuit board, [00:25:13] Speaker 00: The impedance mismatch gets worse because the impedance change between the microstrip on the surface and the pad gets larger. [00:25:21] Speaker 00: You get more metal in the way, changing the impedance. [00:25:24] Speaker 00: You're talking about the BGA? [00:25:26] Speaker 00: I'm talking about the statement on column one. [00:25:29] Speaker 00: I think it's around line 55 or 56, where it says, another example is a substrate used inside a BGA package. [00:25:35] Speaker 00: BGA stands for ball grid array. [00:25:37] Speaker 00: It's referring to the solder balls that, if you look at, [00:25:40] Speaker 00: figure five of the Hall patents are literally balls of solder that add metal, and that makes the impedance problem worse when you do that. [00:25:49] Speaker 00: And we've gone through those examples in our brief. [00:25:56] Speaker 00: Not only does the word integrated circuit appear nowhere in Chin, but the board's only reason to say micro strips were not required in Chin [00:26:05] Speaker 00: was based on a misapplication of claim construction law to reading the prior art. [00:26:10] Speaker 00: It's very clear in the case law that prior art is read for what it teaches, not what it claims. [00:26:17] Speaker 00: And just because claim one of Chin does not mention a microstrip or interconnecting conductor does not mean that every single embodiment relied on by my opponent was a printed circuit board with a microstrip and not an integrated circuit package substrate. [00:26:33] Speaker 00: Now, on inherency, one thing you did not hear my colleague mention on the other side is that the parasitic capacitance was reduced between the layers. [00:26:42] Speaker 00: It's not. [00:26:42] Speaker 00: The only thing in Chin is parasitic capacitance reduced locally at the pad. [00:26:48] Speaker 00: The layer, as you heard in his cross appeal, is something broader that includes more components, and nobody did that analysis. [00:26:55] Speaker 00: And because there's no argument for inherency and nobody did the analysis, there's no basis to affirm on the parasitic capacitance reduction between the claimed layers. [00:27:05] Speaker 00: Now on claims 16 and 17, you just heard an argument that claims 16 does not require a routing layer. [00:27:14] Speaker 00: That is not true. [00:27:15] Speaker 00: They use different terms. [00:27:17] Speaker 00: But they still require the underlying plane to be a signal layer, which routes signals. [00:27:22] Speaker 00: And in Chin, it is a reference plane. [00:27:25] Speaker 00: It is a ground or power plane. [00:27:26] Speaker 00: It does not handle signals. [00:27:28] Speaker 00: And just because it doesn't use the same exact terminology does not mean these planes do not stand or fall together. [00:27:36] Speaker 00: Now turning briefly to the cross appeal. [00:27:39] Speaker 00: The board correctly held that Chin does not disclose same-sized cutouts. [00:27:42] Speaker 00: Judge Rainer, you asked a question just earlier. [00:27:45] Speaker 00: Does Chin require them to be oversized cutouts? [00:27:48] Speaker 00: The answer to that question is, affirmatively, yes. [00:27:51] Speaker 00: And not only is it my view, but it was my opponent's view in their brief at page 69 of their response brief. [00:27:56] Speaker 00: And this is because Chin identifies manufacturing limitations that prevented smaller size cutouts. [00:28:03] Speaker 00: Moreover, there were large variances in fringe capacity that would not be controlled by reducing the size of the cutouts. [00:28:09] Speaker 00: So what do we have? [00:28:10] Speaker 00: We have art that doesn't teach it and says it's impossible. [00:28:14] Speaker 00: The board recognized that for this routing placement limitation, NXP did not provide a motivation in its petition for same size cutouts. [00:28:27] Speaker 00: And you can look no farther than Appendix Page 364 to see how anemic their petitions analysis of this claim was. [00:28:34] Speaker 00: Everything else you heard about smaller, medium, and large, and infinite options or not, that's from the reply brief. [00:28:40] Speaker 00: The board found that waived, and they did not appeal that waiver decision. [00:28:46] Speaker 00: Now, turning to obvious as to try, if you reach that issue at all, the Supreme Court requires finite predictable solutions. [00:28:55] Speaker 00: There's been no showing of finite solutions. [00:28:57] Speaker 00: You have an infinite range of size, value, shapes, and locations. [00:29:00] Speaker 00: They have not specified what that set is, and the board correctly recognized that they would lose under that as well. [00:29:05] Speaker 00: As for the routing placement land limitation, the claim construction they complain of came from their mouth. [00:29:10] Speaker 00: At oral argument, they were asked, is this your position? [00:29:13] Speaker 00: And my NXP confirmed, yes. [00:29:16] Speaker 00: It's in the transcript. [00:29:17] Speaker 00: It's also in their petition to reply. [00:29:19] Speaker 00: Moreover, it's an express claim limitation in claim two. [00:29:21] Speaker 00: It says a routing layer, including routing traces. [00:29:25] Speaker 00: It is not a claim construction, and nothing in this case turns on whether that claim is construed or written as it says to require routing traces. [00:29:36] Speaker 00: With that, you know, I see I'm at the end of my time. [00:29:39] Speaker 00: Are there any questions on the cross of field? [00:29:42] Speaker 03: Thank you, Your Honor. [00:29:43] Speaker 03: I don't think not, Mr. Silver. [00:29:44] Speaker 03: Thank you. [00:29:50] Speaker 03: We'll give you two minutes for a bottle and a cross-peel. [00:29:53] Speaker 01: Thank you, Your Honor. [00:29:54] Speaker 01: I just want to make a couple of points. [00:29:55] Speaker 01: Nowhere does Chen say anything is impossible. [00:29:59] Speaker 01: That is not something Chen says. [00:30:00] Speaker 01: Chen is talking about engineering a solution to a problem and is talking about the context of that problem. [00:30:07] Speaker 01: The motivation to combine [00:30:11] Speaker 01: was in our petition. [00:30:12] Speaker 01: It said appendix 348 and 6181 for the other patent. [00:30:17] Speaker 01: Sorry, this is the motivation for the same size limitations. [00:30:21] Speaker 01: We specifically point out in our petition at 348 and at 6181, same size, less than, greater than. [00:30:29] Speaker 01: The routing layer, the issue there with the routing layer, so in the reply brief, we address the fact that there was confusion, there was uncertainty about the terms, and our Bell's expert [00:30:40] Speaker 01: was unable to determine whether a layer was a routing layer or a reference layer. [00:30:45] Speaker 01: And so that was the issue we were bringing up in our papers. [00:30:48] Speaker 01: But the board issued its claim construction for the first time then on appeal. [00:30:52] Speaker 01: And the issue there is the board then applied a different construction by requiring swapping the two layers as opposed to modifying a layer to add a routing trace. [00:31:02] Speaker 01: Thank you, Your Honors. [00:31:04] Speaker 03: Thank you to both counsel. [00:31:05] Speaker 03: The case is submitted.